Senior/Staff STPG Engineer Product Engineering - Probe

MICRON SEMICONDUCTOR ASIA OPERATIONS PTE LTD

Região Norte

Presencial

BRL 80 000 - 140 000

Tempo integral

Há 4 dias

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Resumo da oferta

MICRON SEMICONDUCTOR ASIA OPERATIONS PTE LTD is seeking a Probe Product Engineer to own probe strategy and silicon learning across pre-silicon to high-volume manufacturing. You will define coverage, establish limits, and drive yield, quality, and test-cost outcomes through close collaboration with Design, DFT, DV, and backend test teams.

You will lead enablement for new products and technology ramps, translating silicon behavior into robust, manufacturable probe strategies that align with

Qualificações

Bachelor’s, Master’s or PhD in Electrical/Electronics Engineering, Computer Engineering with hardware focus, Semiconductor Physics.
Strong fundamentals in semiconductor devices and wafer test.
Experience or interest in silicon learning and device behavior to inform probe/ yield decisions.
Ability to drive structured root-cause analysis across teams.

Responsabilidades

Define and own probe coverage intent by mapping device features and process risks.
Develop probe test flows from first silicon through qualification and high-volume manufacturing.
Establish probe limits/guard-bands based on silicon data and customer specs.
Partner with Design, DFT, DV, Process Integration, Backend Test and Reliability teams.

Conhecimentos

Semiconductor fundamentals

Device behavior analysis

Analytical thinking

Cross-functional collaboration

Communication skills

Formação académica

Electrical/Electronics Engineering (Bachelor/Master/PhD)

Descrição da oferta de emprego

Job Description Summary

The Probe Product Engineer in STPG Product Engineering owns probe strategy and silicon learning at wafer test, spanning pre‑silicon design‑to‑probe staging, first‑silicon bring‑up, qualification, and high‑volume manufacturing (HVM).

This role is accountable for defining probe coverage intent, establishing limits and guard‑bands grounded in silicon behavior, and driving yield, quality, and test‑cost outcomes. The focus is on interpreting design intent, device operation, and process interactions, and translating product risk into robust, manufacturable probe strategies aligned with downstream test and customer requirements.

The engineer works closely with Design, DFT, Design Validation (DV), Process Integration, Backend Test, and Reliability teams to ensure probe solutions are technically sound, scalable, and product‑centric across the lifecycle.

Key Responsibilities

Probe Coverage Strategy & Ownership

Define and own probe coverage intent by mapping design features, device behavior, and process risks into probe observability, screening mechanisms, trims, and guard‑bands.

Define, release, and sustain probe test flows from first silicon through qualification and HVM, ensuring coverage objectives are met without unnecessary test overhead.

Establish probe limits and guard‑bands based on silicon characterization, design intent, and customer specifications, with clear alignment to downstream test.

Lead probe enablement for new product introductions (NPI) and technology ramps, identifying coverage and manufacturability risks early and driving mitigation plans.

Pre‑Silicon Design‑to‑Probe Staging & DFT Readiness

Partner with Design, DFT, and DV teams during pre‑silicon phases to drive effective design‑to‑probe staging.

Review and influence DFT architecture, test hooks, observability, redundancy, and trim structures to enable efficient and manufacturable probe coverage.

Participate in pre‑silicon verification and simulation reviews to reduce first‑silicon debug risk.

Define probe coverage intent early and ensure continuity from design features through probe and downstream test (shift‑left learning).

First Silicon Bring‑Up & Device Characterization

Support first‑silicon bring‑up using engineering probe platforms and lab‑based characterization setups.

Perform silicon and device‑level characterization (parametric behavior, margins, trims, stress response) to inform probe limits and screening strategy.

Correlate early silicon behavior with probe results to validate coverage intent, identify gaps, and eliminate redundant content.

Provide early silicon learning to accelerate probe flow stabilization and yield ramp.

Yield, Quality & Reliability Enablement

Drive wafer‑level yield learning, bin definitions, and failure‑mode analysis at probe.

Enable intrinsic and extrinsic screening strategies in collaboration with Reliability teams.

Provide structured, data‑backed feedback to Fab, Process Integration, Design, and DV teams to close learning loops efficiently.

Test Efficiency & Cost Optimization

Drive test efficiency improvements through coverage right‑sizing and flow optimization, aligned to product and market needs.

Support wafer‑level speed (WLS) activities as part of broader probe optimization efforts.

Balance coverage, yield, quality, and cost trade‑offs using silicon data and product risk understanding.

Data, Analytics & AI Enablement

Leverage probe, inline, and reliability data for yield analysis, anomaly detection, and decision support.

Contribute to AI/ML initiatives such as predictive probe, smart sampling, and test optimization.

Apply data‑driven insights to continuously improve probe effectiveness and efficiency.

Artificial Intelligence

Using, applying, and leveraging AI, identify opportunities to streamline workflows, optimize processes, and support innovation by incorporating AI-driven solutions and enabling data‑driven decision‑making across projects and teams

Required Qualifications

Bachelor’s, Master’s degree, or Phd in Electrical / Electronics Engineering, Computer Engineering (with strong hardware, circuits, or semiconductor focus), Semiconductor Physics, or related field.