RTL Engineer

Capgemini; Fundão; Presencial; BRL 167 000 - 234 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Health and life insurance

Hybrid work model

Training & certifications

Resumo da oferta

Capgemini Engineering in Brazil is seeking a Senior RTL Engineer to drive digital design from architecture to tape-out, delivering high-performance, power-efficient products. You will support system architecture, define microarchitectures, and implement RTL with Verilog, SystemVerilog, or VHDL.

Engage with Verification, Synthesis, STA, Physical Design, and DFT teams to meet timing, power, and area targets. Hybrid work and career growth opportunities are offered.

Qualificações

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 6+ years of RTL/ASIC/SoC/VLSI design experience.
• Proven experience with Verilog/SystemVerilog and/or VHDL.
• Experience in microarchitecture definition for complex digital blocks.
• Strong knowledge of SoC design methodologies and integration.
• Hands-on with Lint, CDC, and Low Power design methodologies.
• Familiar with synthesis flows and Static Timing Analysis (STA).
• Knowledge of CPU architectures such as ARM, RISC-V, or x86.
• Experience with Python, Perl, or C scripting.
• Understanding of verification methods and design flows.

Responsabilidades

• Perform feasibility studies to support system architecture and interface specs.
• Define and develop microarchitectures for complex digital blocks and SoCs.
• Implement RTL designs using Verilog, SystemVerilog, or VHDL.
• Execute RTL quality checks including lint, CDC, and Low Power checks.
• Develop timing constraints and support synthesis and timing closure.
• Collaborate with Verification, Synthesis, STA, Physical Design, and DFT teams.
• Support bring-up, integration, and tape-out activities.
• Create automation scripts and design flows to improve efficiency.
• Participate in technical reviews and process improvements.

Conhecimentos

RTL design

ASIC

SoC

VLSI design

Verilog

SystemVerilog

VHDL

Lint

CDC

Low Power design

STA

Python

Perl

C

ARM

RISC-V

x86

Formação académica

Bachelor's in Electrical Engineering or Computer Engineering

Master's degree (advantage)

Descrição da oferta de emprego

CAPGEMINI ENGINEERINGAt Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.YOUR ROLEAs a Senior RTL Engineer, you will be responsible for driving digital design activities from architecture definition through tape-out, ensuring the successful delivery of high-performance and power-efficient products.In this role, you will:Perform feasibility studies to support system architecture definition, requirements analysis, and interface specification.Define and develop microarchitectures for complex digital blocks and SoCs.Implement RTL designs using Verilog, SystemVerilog, or VHDL.Execute RTL quality checks, including Lint, CDC, and Low Power verification.Develop timing constraints and support synthesis and timing closure activities.Collaborate closely with Verification, Synthesis, STA, Physical Design, and DFT teams to achieve functionality, performance, power, and area targets.Support design bring-up, integration, and tape-out activities.Create and maintain automation scripts, design flows, and engineering tools to improve development efficiency.Participate in technical reviews and contribute to continuous improvement initiatives.YOUR PROFILEBachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.6+ years of experience in RTL, ASIC, SoC, or VLSI design.Strong knowledge of Verilog, SystemVerilog, and/or VHDL.Proven experience in microarchitecture definition and complex digital design development.Solid understanding of SoC design methodologies and integration.Hands-on experience with Lint, CDC, and Low Power design methodologies.Good knowledge of synthesis flows and Static Timing Analysis (STA).Familiarity with CPU architectures and instruction sets such as ARM, RISC-V, or x86.Experience with scripting and programming languages such as Python, Perl, or C.Understanding of verification methodologies and design flows.Strong problem-solving skills and attention to detail.Excellent communication skills and ability to work effectively in multicultural and multidisciplinary environments.WHAT YOU’LL LOVE ABOUT WORKING HEREJoin a multicultural and inclusive team environment.Enjoy a supportive atmosphere promoting work life balance.Hybrid work.Your career growth is central to our mission. Our array of career growth programs and diverse professionals are crafted to support you in exploring a world of opportunities.Access valuable training and certifications in cutting edge technologies.Engage in exciting national and international projects.Health and life insurance.Referral program with bonuses for talent recommendations.Great office locations.ABOUT CAPGEMINICapgemini is an AI-powered global business and technology transformation partner, delivering tangible business value. We imagine the future of organizations and make it real with AI, technology and people. With our strong heritage of nearly 60 years, we are a responsible and diverse group of 420,000 team members in more than 50 countries. We deliver end-to-end services and solutions with our deep industry expertise and strong partner ecosystem, leveraging our capabilities across strategy, technology, design, engineering and business operations.