Intern: Application Engineering - Digital Verification & Simulation/VIP

Cadence Design Systems; Belo Horizonte; Presencial; BRL 13 000 - 20 000; Tempo parcial

Vantagens oferecidas por esta oferta de emprego

Competitive benefits

Resumo da oferta

Cadence Design Systems in Belo Horizonte, Brazil, is seeking an Application Engineering Intern for Digital Verification & Simulation (VIP). You will join the TFO-SVG team, supporting RTL verification products and working with Cadence DVIP tools, under mentorship, 20 hours/week.

You will gain experience in RTL verification, scripting with TCL/Python, and collaborating with R&D to deliver solutions for customers. Graduation expected mid-2027.

Qualificações

• Pursuing a bachelor’s degree in Electrical, Computer, Electronics or related fields with expected graduation mid-2027.
• Must demonstrate strong problem-solving and communication skills.
• Curiosity and willingness to learn digital verification methodologies.

Responsabilidades

• Provide technical support to customers and field personnel for RTL verification solutions.
• Conduct root cause analysis and drive issue resolution with RD teams.
• Develop and run test cases, and implement workarounds and R&D fixes.
• Collaborate with RD using established protocols and document findings.
• Author application notes and contribute to documentation improvements.
• Use TCL and Python to develop flows, automate tasks, and enhance methodologies.

Conhecimentos

Problem-solving

Interpersonal communication

Learning attitude

RTL exposure (Verilog/VHDL)

TCL/Python scripting

Formação académica

Ongoing bachelor's in Electrical/Computer Engineering or related

Ferramentas

RTL: Verilog/VHDL

TCL

Python

Descrição da oferta de emprego

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence Design Systems Inc. is looking for a motivated Application Engineering Intern: Digital Verification & Simulation - VIP to work with us in Belo Horizonte, Brazil.

As an Intern: Application Engineering - Digital Verification & Simulation (VIP), you will be trained to become an expert in Digital Verification & Simulation methodologies in the System Verification Group - Technical Field Operations (TFO-SVG) in Belo Horizonte. The TFO-SVG group works with Xcelium, Palladium, Protium, Jasper, VIPs, Perspec, and other Cadence Digital Functional Verification tools.

The application engineers provide technical support, enabling customers to effectively deploy our industry-leading technology, focused on RTL-level verification products. You will be in a Digital Verification & Simulation focused team working with our Verification IP Solutions, complimentary tools, and its customers to understand their needs and provide guidance on the best technologies and methodologies to enable their success, coming up with innovative solutions to address the industry’s most challenging problems.

Job Description:

• Activities focused on the Functional Verification field as mentioned above, mentored by experienced colleagues, and reporting to higher management.
• Provide technical support to customers and field personnel in RTL verification solutions focused on the Cadence Verification IP solutions and supporting technologies.
• Conduct root cause analysis and provide resolution to customer technical issues.
• Help to develop and run test cases to verify problems, create workarounds when possible, test and deliver R&D fixes.
• Close collaboration with R&D on issues using established protocols.
• Author application notes and help provide feedback on documentation.
• Help use scripting languages like TCL and Python for flow development, automation and enhancing design methodologies.

Requirements:

• Ongoing bachelor’s in Electrical Engineering, Computer Engineering, Electronics Engineering, Control and Automation Engineering, Systems Engineering, Computer Science, Information Systems, Computational Mathematics, or related areas.
• Graduating in mid 2027
• Good problem-solving skills.
• Strong inter-personal and communication skills.
• A strong interest in learning the technical topics mentioned above.

Nice to have Skills

• Exposure to RTL (Verilog or VHDL) is a plus.
• Experience in scripting languages such as TCL and Python is a plus.

Additional Job Details:

• Employment category: Internship.
• Employment term: 20 hours/week.
• Competitive benefits.
• Av. do Contorno 5800, Savassi, Belo Horizonte, Minas Gerais

About Cadence Design Systems:

At Cadence, we hire and develop leaders and innovators who want to impact the world of technology. Cadence has been nominated as a Great Place to Work globally and in Brazil and is also a Fortune 100 Best Companies to Work For.

Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information, access http://www.cadence.com .

We’re doing work that matters. Help us solve what others can’t.