Sustainability Assessment on Power Semiconductor Device Manufacturing

Imec; Vlaams-Brabant; On-site; EUR 12,000 - 17,000; Full time

Benefits offered by this job

Imec allowance

Job summary

Imec invites PhD or Master students to join a Sustainability Assessment internship focusing on manufacturing of power semiconductor devices. You will build and extend a process-flow model across generations and technologies, collecting evidence and documenting assumptions.

In this role you will implement variants in the imec.netzero modelling environment, run cradle-to-gate impact calculations, and compare generations to identify main contributors.

Qualifications

• Required educational background in Chemistry/Chemical Engineering, Electrotechnics/Electrical Engineering, Nanoscience & Nanotechnology or Physics.
• Ability to review and map process flows for power semiconductor devices.
• Experience in breaking down processes into modular components and creating generation-specific process-flow tables.

Responsibilities

• Review and map existing process flows for selected power semiconductor devices and identify key manufacturing steps and differences between generations.
• Break down process flows into reusable modules such as wafer preparation, epitaxy, isolation, implantation, thermal processing, metallization, passivation, and other steps.
• Create generation-specific process-flow tables with parameters like wafer size, material consumption, layer thickness, and process conditions.
• Collect and document evidence behind process parameters and identify data uncertainties.
• Implement selected process-flow variants in the imec.netzero modelling environment and run environmental impact calculations.
• Compare technology generations to quantify cradle-to-gate environmental impact.
• Summarize and visualize results, highlighting main contributors and data gaps.

Skills

process-flow modeling

environmental impact assessment

data collection

visualization

Education

Chemistry

Chemical Engineering

Electrotechnics/Electrical Engineering

Nanoscience & Nanotechnology

Physics

Tools

imec.netzero modelling environment

Job description

Sustainability Assessment on Power Semiconductor Device Manufacturing

Explore how power semiconductor manufacturing evolves across generations—and use process‑flow modeling to uncover how each technological shift reshapes its environmental footprint.

Power semiconductor device manufacturingspans multiple material platforms, device architectures, voltage classes, waferformats, and integration schemes. The next step is to transform thesetechnology-specific models into a consistent generational framework thatenables like-for-like comparison while preservingtheprocessdifferences that define each platform.

In this internship, the student will build and extend a process‑flow model for power semiconductor manufacturing across different device generations and technologies. The student will:

• Review and map existingprocess flows for selected power semiconductor devices and identifythe key manufacturing steps and differences between technologygenerations.
• Break down the processflows into reusable modules such as wafer preparation, epitaxy,isolation, implantation, thermal processing, metallization, passivation,and other relevant manufacturing steps.
• Creategeneration-specific process‑flow tables, defining parameters such aswafer size, material consumption, layer thickness, process conditions,number of process steps, and other relevant assumptions.
• Collect and document theevidence behind process parameters and assumptions , and identify the main sources of uncertainty where data are not available.
• Implement selectedprocess‑flow variants in the imec.netzero modelling environment and runenvironmental impact calculations.
• Compare differenttechnology generations to quantify how changes in device architectureand manufacturing processes affect cradle‑to‑gate environmental impact.
• Summarize and visualizethe results, identifying which process modules and technology changesare the main contributors to environmental impact and where further dataor model refinement is needed.

The outcome will be a reusable process‑flow mode l ling framework that can be extended to additional power semiconductor generations and technologies, enabling systematic comparison of their manufacturing‑related environmental footprints.

Type of internship: PhD internship, Master internship

Duration: 1 year

Required educational background: Chemistry/Chemical Engineering, Electrotechnics/Electrical Engineering, Nanoscience & Nanotechnology, Physics

Supervising scientist(s): Joo Hyoung Kim

The reference code for this position is 2026-INT-257.

Imec allowance will be provided.