Senior PVD Process Developer for Next‑Gen CMOS

Imec; Vlaams-Brabant; On-site; EUR 80,000 - 110,000; Full time

Job summary

Imec in Leuven, Belgium, seeks a (Senior) PVD Process Development Engineer to advance next-generation PVD processes for CMOS logic, memory and heterogeneous integration in a state-of-the-art 300/200mm semiconductor fabrication environment.

You will lead DOE studies, develop and optimize deposition processes (magnetron, reactive, RF and DC sputtering), and characterize films with XRD, XRR, SEM/TEM, XPS, AFM and more, collaborating with integration teams to transfer developed processes into device

Qualifications

• Minimum 4 years of industrial or advanced research experience in semiconductor process development.
• Strong hands-on expertise in PVD technologies (magnetron, reactive, RF/DC sputtering).
• Familiarity with ALD, CVD, SSE, RPC.
• Excellent communication skills and ability to work in multidisciplinary teams.
• Knowledge of Python, Matlab, JMP, Minitab, Klarity, E3/FDC, etc. is a plus.

Responsibilities

• Develop and optimize PVD processes for CMOS, Logic, Memory and other cutting-edge technologies.
• Lead process development activities from concept through technology qualification.
• Design and execute DOE to establish process windows and achieve target performance metrics.
• Characterize deposited films using advanced metrology techniques including XRD, XRR, SEM/TEM, XPS, AFM.
• Analyze experimental data and collaborate with process integration teams to implement into device flows.
• Interface with equipment suppliers, material vendors and customers as required.

Skills

Analytical thinking

Troubleshooting

Communication skills

Multidisciplinary teamwork

Python / Matlab knowledge

Education

Master in Science or Engineering

Tools

Magnetron sputtering

Reactive sputtering

RF sputtering

DC sputtering

Ion-assisted deposition

ALD

CVD

SSE

RPC

Job description

Imec in Leuven, Belgium, seeks a (Senior) PVD Process Development Engineer to advance next-generation PVD processes for CMOS logic, memory and heterogeneous integration in a state-of-the-art 300/200mm semiconductor fabrication environment.

You will lead DOE studies, develop and optimize deposition processes (magnetron, reactive, RF and DC sputtering), and characterize films with XRD, XRR, SEM/TEM, XPS, AFM and more, collaborating with integration teams to transfer developed processes into device