(Senior) PVD Process Development Engineer

imec

Heverlee

On-site

EUR 75,000 - 110,000

Full time

3 days ago
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Job summary

imec is seeking a highly motivated (Senior) PVD Process Development Engineer to advance physical vapor deposition for CMOS technologies in a state-of-the-art 300/200mm semiconductor fabrication environment in Belgium.

You will work with cross-disciplinary teams to develop and optimize PVD processes, characterize films using advanced metrology, and drive technology qualification from concept through implementation.

Qualifications

Responsibilities

  • Tool selection and take part in tool procurement process for advance semiconductor technology development.
  • Develop and optimize advanced PVD processes for CMOS, Logic, Memory and other cutting-edge technologies which includes: Metal deposition (standard and emerging materials); Barrier and liner layers; Contacts and interconnect applications; Advanced gate stack and BEOL metallization schemes.
  • Lead process development activities from concept through technology qualification.
  • Design and execute DOE (Design of Experiments) to establish process windows and achieve target performance metrics.
  • Characterize deposited films using advanced metrology techniques including: XRD, XRR, SEM/TEM, XPS, AFM, Four-point probe, Stress and adhesion measurements, Ellipsometry.
  • Analyze experimental data and derive physical understanding of film growth mechanisms, nucleation behavior, and plasma-material interactions.
  • Collaborate with process integration teams to ensure successful implementation of developed processes into device process flows.
  • Interface with equipment suppliers, material vendors, research partners, and customers as required in a dynamic multidisciplinary and multicultural environment.
  • As opportunities arise, innovate new techniques of characterization that align with the Imec's technology roadmap.

Job description

What you will do

We are seeking a highly motivated (Senior) PVD Process Development Engineer to join our advanced semiconductor thin film deposition and diffusion technology development team (DDDEV). The successful candidate will play a key role in developing next-generation Physical Vapor Deposition (PVD) processes for advanced CMOS technology nodes, supporting cutting-edge logic, memory, and heterogeneous integration applications.

This position offers the opportunity to work in a state-of-the-art 300/200mm semiconductor fabrication environment, collaborating with integration, process, equipment, metrology, and reliability experts to enable future semiconductor technologies.

As a PVD process development engineer, you will be responsible for tools and processes:

  • Tool selection and take part in tool procurement process for advance semiconductor technology development.
  • Develop and optimize advanced PVD processes for CMOS, Logic, Memory and other cutting-edge technologies which includes:
    • Metal deposition (standard and emerging materials)
    • Barrier and liner layers
    • Contacts and interconnect applications.
    • Advanced gate stack and BEOL metallization schemes
  • Lead process development activities from concept through technology qualification.
  • Design and execute DOE (Design of Experiments) to establish process windows and achieve target performance metrics.
  • Characterize deposited films using advanced metrology techniques including:
    • XRD
    • XRR
    • SEM/TEM
    • XPS
    • AFM
    • Four-point probe
    • Stress and adhesion measurements
    • Ellipsometry
  • Analyze experimental data and derive physical understanding of film growth mechanisms, nucleation behavior, and plasma-material interactions.
  • Collaborate with process integration teams to ensure successful implementation of developed processes into device process flows.
  • Interface with equipment suppliers, material vendors, research partners, and customers as required in a dynamic multidisciplinary and multicultural environment.
  • As opportunities arise, innovate new techniques of characterization that align with the Imec's technology roadmap.
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