Senior DFT Architect for Next-Gen SoCs

imec; Vlaams-Brabant; Sur place; EUR 90 000 - 120 000; Plein temps

Résumé du poste

imec, based in Leuven, Belgium, seeks a Senior DFT Engineer to shape next-gen semiconductors by innovating in Design-for-Test. You will develop cutting-edge integrated circuits in a world-class R&D environment, ensuring testability, quality and performance of complex chip designs.

You will architect DFT solutions for SOCs, negotiate requirements with teams and customers, and implement techniques across large low-power designs in advanced nodes.

Qualifications

• 5+ years of experience in DFT insertion and ATPG.
• Basic fluency with Verilog/VHDL to write test logic when needed.
• Experience as a DFT owner of sub-systems including insertion and verification of DFT structures.
• Experience with DFT integration of complex PHY blocks (PCIe, UCIe, LPDDR5, etc.).
• Hands-on experience with defining SDC constraints for DFT and inserting/verifying boundary scan, compression, MBIST/repair, OPCG/OCC, ATPG, fault coverage improvement, test debug for large low-power designs.

Responsabilités

• Architect DFT solutions for SOCs with multiple sub-blocks and complex IPs.
• Coordinate/Negotiate DFT requirements with project teams and customers.
• Implement and validate innovative DFT techniques on SOCs and subsystems.
• Define timing constraints for DFT test-modes.
• Insert boundary scan, compression, MBIST/repair, OPCG/OCC for large-scale designs.

Connaissances

DFT insertion

ATPG

Verilog/VHDL

Boundary scan

SB/MBIST

OCG/OCC

ATPG fault coverage

TCL scripting

Outils

Tessent

Genus/Modus

Tessent SSN

IEEE1838

Description du poste

imec, based in Leuven, Belgium, seeks a Senior DFT Engineer to shape next-gen semiconductors by innovating in Design-for-Test. You will develop cutting-edge integrated circuits in a world-class R&D environment, ensuring testability, quality and performance of complex chip designs.

You will architect DFT solutions for SOCs, negotiate requirements with teams and customers, and implement techniques across large low-power designs in advanced nodes.