Physical Design Engineer

IC Resources; Antwerpen; Sur place; EUR 65 000 - 90 000; Plein temps

Résumé du poste

IC Resources in Antwerp is seeking a hands-on Physical Design Engineer to join their semiconductor R&D team. The role covers RTL-to-GDS flow, implementation, optimization and backend methodology development, with close collaboration to analog and digital design teams.

You will execute the full digital backend from RTL to GDS, including synthesis, floorplanning, CTS, STA, and LEC, while developing scalable flows and automation scripts. This position is on-site in Antwerp.

Qualifications

• Bachelor’s degree or above in microelectronics or related field.
• Experience with the complete digital backend flow from RTL to GDS.
• Experience with industry-standard EDA tools.
• Proficiency in scripting languages (Tcl, Python).
• Experience with Cadence tools is preferred.

Responsabilités

• Execute the complete digital backend flow from RTL to GDS, including synthesis, floorplanning, power planning, place & route, clock tree synthesis (CTS), static timing analysis (STA) and logic equivalence checking (LEC).
• Provide innovative solutions to reach product targets and drive performance, power and area optimizations.
• Develop, maintain and enhance backend methodologies, flows and automation scripts.
• Collaborate closely with the analog team and the digital design and verification engineers to resolve implementation challenges and successfully complete the project.
• Participate in design/architecture reviews and risk assessments from a physical implementation perspective.

Connaissances

RTL to GDS flow

Tcl scripting

Python scripting

Digital backend flow

Formation

Bachelor’s degree in microelectronics or related fields

Outils

Cadence tools

EDA tools

Description du poste

Physical Design Engineer - Antwerp

This client is looking for a Physical Design Engineer to join their semiconductor R&D team in Antwerp, working on the implementation of complex digital circuitry for advanced imaging technologies.

This is a hands‑on Physical Design Engineer position covering the RTL‑to‑GDS flow, with scope to work across implementation, optimisation and backend methodology development.

Key responsibilities:

• Execute the complete digital backend flow from RTL to GDS, including synthesis, floorplanning, power planning, place & route, clock tree synthesis (CTS), static timing analysis (STA) and logic equivalence checking (LEC).
• Provide innovative solutions to reach product targets and drive performance, power and area optimizations.
• Develop, maintain and enhance backend methodologies, flows and automation scripts.
• Collaborate closely with the analog team and the digital design and verification engineers to resolve implementation challenges and successfully complete the project.
• Participate in design/architecture reviews and risk assessments from a physical implementation perspective.

Position Qualifications

• Bachelor’s degree or above in microelectronics or related fields.
• Experience with the complete digital backend flow from RTL to GDS.
• Experience with industry-standard EDA tools.
• Proficiency in scripting languages (Tcl, Python).
• Experience with Cadence tools is preferred