Physical ASIC Design Implementation Engineer

Engibex; Vlaams-Brabant; Sur place; EUR 65 000 - 95 000; Plein temps

Résumé du poste

Engibex seeks a Physical Implementation engineer to lead full backend flows for chip designs from netlist-in to GDSII-out, spanning from ensure top-level to block-level blocks in nodes from N2 to 180nm. You will drive the Cadence Innovus Place&Route flow and collaborate with the PD team to meet sign-off targets.

The role requires close interaction with customers, partitioning top-level SDC into timing budgets, and providing technical guidance on specifications throughout the chip design cycle.

Qualifications

• Experience setting up the flow for the library set and foundry node used.
• Experience setting-up low power design (UPF) and debug SDC file.
• Knowledge in Floorplanning & power grid design for top-level as well as blocks.
• Place, CTS & Routing.
• Solve setup & hold violations.
• Sign-off extraction (SPEF/QUANTUS), timing (Tempus), Power analysis (Voltus).
• Physical verification (DRC, ERC, LVS, ANT), Logic equivalence check.

Responsabilités

• Direct contact with our customers for future projects.
• Full understanding of the Cadence Innovus Place&Route flow.
• Take the lead for partitioning and splitting the top level SDC into timing budget requirements/constraints of sub-blocks.
• Work with the Physical Design implementation team to drive signoff closure for tape-out.
• Technical voice to the customer to discuss specifications.

Connaissances

Flow setup

UPF low power design

Floorplanning

Place CTS Routing

Timing closure

Sign-off methods

Physical verification

Outils

Cadence Innovus Place&Route

SPEF/QUANTUS

Tempus

Voltus

DRC/ERC/LVS/ANT

Description du poste

About company

We are a Belgian engineering consulting firm that assists SMEs and large industrial organizations in bringing their innovation and R&D initiatives to life.

Job Description

Physical Implementation engineer for full backend (P&R) projects from netlist-in to GDSII-out flow, for toplevel chips aswell as blocklevel blocks in technologies ranging from N2 to 180nm. This with the full understanding of the complete Cadence Innovus Place&Route flow.

• Direct contact with our customers for future projects.
• Full understanding of the complete Cadence Innovus Place&Route flow.
• Take the lead for partitioning and split the top level SDC file into timing budget requirements/constraints of the sub-blocks.
• Work directly with the Physical Design implementation team during the entire chip design cycle to drive signoff closure for tape-out.
• Technical voice to the customer to discuss his specifications

Required qualifications

• Experience in setting-up the flow for the specific library set and foundry node used
• Experience in setting-up low power design (UPF) and debug sdc file
• Knowledge in Floorplanning & power grid design for toplevel aswell as blocks
• Place, CTS & Routing
• Solve setup & hold violations
• Sign-off extraction (SPEF/QUANTUS) , timing (TEMPUS), Power analysis (VOLTUS)
• Physical verification (DRC, ERC, LVS, ANT), Logic equivalent check