Lead Digital ASIC/SoC Architect: From System to Silicon

DSJ Global; Brussel Hoofdstad; On-site; EUR 110,000 - 170,000; Full time

Job summary

DSJ Global is seeking an experienced Principal Digital ASIC / SoC Architect to own the digital ASIC/SoC architecture from concept to silicon. You will translate system requirements into detailed silicon architectures, lead HW/SW partitioning, and direct external partners through the full ASIC lifecycle.

The role demands strong technical leadership and proven decision-making across power, performance and area trade-offs.

Qualifications

• Extensive experience in digital ASIC/SoC architecture and development.
• Ability to translate system requirements into silicon architectures.
• Knowledge of processors, DSPs, memory, interfaces and digital subsystems.
• Strong HW/SW partitioning and decision-making for architecture trade-offs.
• Experience with FPGA prototyping, modelling and verification.

Responsibilities

• Own the digital ASIC/SoC architecture from requirements through silicon acceptance.
• Translate high-level requirements into detailed architectures and specs.
• Define architectures including processors, DSPs, interfaces and compute functions.
• Lead hardware/software partitioning and IP selection decisions.
• Evaluate approaches including custom silicon and external IP.
• Lead trade-offs across power, performance, area, cost and risk.
• Define deliverables for external partners and govern outsourced development.
• Lead architecture reviews and manage technical risks early.
• Support validation using modelling, simulation, formal verification, FPGA prototyping.

Skills

Digital ASIC/SoC architecture

Hardware/software partitioning

RTL to silicon lifecycle

FPGA prototyping

System requirements to silicon

Leadership & technical authority

Tools

FPGA/HDL modelling tools

Simulation/verification tools

Formal verification

Job description

DSJ Global is seeking an experienced Principal Digital ASIC / SoC Architect to own the digital ASIC/SoC architecture from concept to silicon. You will translate system requirements into detailed silicon architectures, lead HW/SW partitioning, and direct external partners through the full ASIC lifecycle.

The role demands strong technical leadership and proven decision-making across power, performance and area trade-offs.