Lead ASIC Verification Engineer - Mixed-Signal SoCs

Vivid Resourcing Ltd; Vlaams-Brabant; Sur place; EUR 65 000 - 90 000; Plein temps

Avantages offerts par ce poste

Salary & benefits package

Résumé du poste

Vivid Resourcing Ltd is seeking an ASIC Engineer to join a multidisciplinary semiconductor development team in Leuven. You will verify and develop SoCs, IPs and subsystems, spanning analogue and digital domains, with hands-on simulation, verification and debugging.

You will own critical technical activities, help develop team methodologies and mentor junior engineers, while contributing to automation and verification infrastructure improvements.

Qualifications

• Proven experience in ASIC design, verification or mixed-signal verification.
• Strong understanding of digital and analogue design principles.
• Hands-on experience with simulation, verification and debugging of complex IC designs.
• Strong knowledge of SystemVerilog and UVM.
• Experience with behavioural modelling languages such as Verilog-A, Verilog-AMS, SV-RNM or VHDL-AMS.
• Experience with SPICE and digital simulation environments.
• Good knowledge of EDA tools such as Cadence and/or Synopsys.
• Experience developing verification environments, testbenches and simulation flows.
• Programming or scripting experience with Python, Perl, TCL or similar.
• Strong analytical and problem-solving skills, particularly when debugging complex design issues.

Responsabilités

• Develop and improve simulation and verification methodologies and flows.
• Review technical specifications and develop verification plans.
• Manage BOMs, netlists and associated verification setups.
• Work closely with analogue and digital design teams to track design changes and updates.
• Run and debug SPICE-based and digital simulations for SoCs, IPs and subsystems.
• Review simulation environments and ensure appropriate test conditions are being applied.
• Analyse simulation results and waveforms to identify functional issues and determine root causes.
• Develop behavioural models using Verilog-A/AMS, SV-RNM and/or VHDL-AMS.
• Develop and optimise testbenches using tools such as Cadence Xcelium, Virtuoso and Synopsys platforms.
• Contribute to regression, automation and verification infrastructure improvements.
• Develop scripts for tasks such as simulation management, log parsing and result analysis.
• Document verification results, debug findings and methodology updates.
• Take ownership of critical technical tasks and support the planning and distribution of work within the team.
• Provide technical guidance, mentoring and knowledge sharing to other engineers.

Connaissances

SystemVerilog

UVM

ASIC verification

Verilog-A/AMS

Python scripting

C/C++ basics

Outils

Cadence Xcelium

Virtuoso

Synopsys platforms

Description du poste

Vivid Resourcing Ltd is seeking an ASIC Engineer to join a multidisciplinary semiconductor development team in Leuven. You will verify and develop SoCs, IPs and subsystems, spanning analogue and digital domains, with hands-on simulation, verification and debugging.

You will own critical technical activities, help develop team methodologies and mentor junior engineers, while contributing to automation and verification infrastructure improvements.