Analog Layout engineer with 28nm experience

Chipright Inc.

Belgique

On-site

EUR 65,000 - 90,000

Full time

14 days+

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Job summary

Chipright Inc. is seeking an Analog Layout engineer with 28nm experience to lead full custom layout design efforts for analog blocks and IO ring integration.

The role requires dong chip-level checks and top-level verifications (DRC/LVS/EM/IR) and preparing layout closure reports as per project needs.

Qualifications

  • Expert in designing Analog/RF layouts.
  • Experience with tape-out in 28nm technology.
  • Awareness of layout effects for 28nm technology.
  • Ability to advise circuit design based on layout expertise.
  • Knowledge of Virtuoso GXL and tape-out steps.

Responsibilities

  • Perform full custom analog layout design for various blocks.
  • Carry out chip-level checks after connecting designed blocks and IO ring.
  • Conduct block-level and top-level verifications (DRC, LVS, EM/IR, etc.).
  • Prepare layout design closure reports as required.

Skills

Analog layout
RF layout
Tape-out experience
Layout verification

Tools

Virtuoso GXL

Job description

Analog Layout engineer with 28nm experience

Salary: very attractive rate

Location: N/A

Contract

Analog Layout EngineerFull Custom Layout Design of various Analog blocks, taking into consideration the specifications and guidelines required for the Design, floor planning and performing layout validations.The assignment

  • Full Custom Analog Layout Designer having experience of designing various Analog Blocks for various technologies.
  • The candidate should be able to perform Chip Level checks after connecting various designed blocks and Top Level routing after creating IO ring.
  • Block level and Top level verifications like DRC,LVS,EM/IR etc.
  • Preparation of Layout Design closure reports as per requirements.
Required knowledge and skills
  • Candidate applying for this position should be an expert in designing Analog/RF layouts.
  • Should have prior experience for tape out in TSMC 28nm technology.
  • Should be aware of all the layout related effects for this technology.
  • Should be able to help Circuit Design Engineer take necessary decision based on his layout expertise for this technology.
  • Should have the required knowledge for Virtuoso GXL, and all the steps/ layout verifications required for GDS tape out.

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