Aerospace ASIC Design Engineer: RTL, FPGA & Verification

Vivid Resourcing; Vlaams-Brabant; Sur place; EUR 55 000 - 90 000; Plein temps

Résumé du poste

A Leuven-based aerospace technology company is seeking an ASIC Design Engineer to join a high‑caliber R&D team. You will design, develop and verify digital hardware, contributing across the ASIC lifecycle while collaborating with experienced engineers.

You will work on RTL designs, logic synthesis, timing closure and use industry‑standard EDA tools. A Master’s or PhD in electronics or related field is expected, with strong English skills and a track record in ASIC, FPGA or digital hardware

Qualifications

• Master’s degree or PhD in Electronics, Electrical Engineering, CS or Applied Physics.
• Experience with ASIC, FPGA or digital hardware design.
• Proficiency in RTL design and digital logic; VHDL or Verilog.
• Experience with simulation, verification, synthesis or timing analysis.
• Programming in Python, MATLAB, SystemC or similar.
• Professional working proficiency in English.

Responsabilités

• Design and develop digital ASIC solutions.
• Create and maintain RTL designs.
• Develop, simulate and verify digital designs.
• Work through logic synthesis and timing closure.
• Analyse and resolve complex technical challenges.
• Use industry-standard EDA tools during the development process.
• Document designs and contribute to verification activities.
• Collaborate with technical leads and engineers across the wider R&D organisation.
• Contribute to the development and improvement of design methodologies.

Connaissances

ASIC Design

RTL Design

FPGA

Logic Synthesis & Timing Closure

MATLAB / Python / SystemC

Git

VHDL or Verilog

English proficiency

Formation

Master’s degree or PhD in Electronics/Electrical Engineering/CS

Outils

EDA tools

Description du poste

A Leuven-based aerospace technology company is seeking an ASIC Design Engineer to join a high‑caliber R&D team. You will design, develop and verify digital hardware, contributing across the ASIC lifecycle while collaborating with experienced engineers.

You will work on RTL designs, logic synthesis, timing closure and use industry‑standard EDA tools. A Master’s or PhD in electronics or related field is expected, with strong English skills and a track record in ASIC, FPGA or digital hardware