Digital Signal Processing ASIC R&D Engineer

Keysight Technologies SAles Spain SL.; Vlaams-Brabant; Sur place; EUR 50 000 - 75 000; Plein temps

Résumé du poste

Keysight Technologies SAles Spain SL. in Leuven, Belgium is seeking a Digital Signal Processing ASIC R&D Engineer to work within an international team. The ideal candidate will research and develop DSP algorithms impacting future products.

Candidates should possess a Master’s degree or PhD in relevant fields and have strong English proficiency. Experience with EDA tools and a Belgian work permit are required. Join our team to innovate and push the boundaries of technology.

Qualifications

• Master’s degree or PhD in Electronics and Chip Design, Information Systems & Signal Processing, Computer Sciences, Applied Physics or equivalent.
• Full professional working proficiency in spoken and written English.
• Belgian work permit required.

Responsabilités

• Research, design and verify digital/DSP and mixed signal ASICs.
• Code, verify and document designs, synthesizing them to timing closure.

Connaissances

Digital Signal Processing

ASIC design

Python

Matlab

Team collaboration

Formation

Master’s degree or PhD in Electronics and Chip Design

Outils

EDA tools

VHDL or Verilog

Linux

Git

Description du poste

Overview

Keysight Hardware Labs ASIC Team in Leuven, Belgium (EU) is located next to the Leuven railway station.

The Labs is a central R&D organization, enabling rapid market launch of breakthrough products. We focus on Digital Signal Processing (DSP) and Mixed Signal Application Specific Integrated Circuits (ASICs) that drive performance and value of new products.

In our team, applied research and development for these ASICs is the core of our specialty and expertise. Bringing the algorithm to silicon is what we do daily.

Responsibilities

Digital Signal Processing ASIC R&D Engineer will work within an international team to explore and design DSP algorithms and digital designs, using state‑of‑the‑art EDA tools to directly impact key specifications of Keysight's future products.

• Research, design and verify digital/DSP and mixed signal ASICs that meet Test & Measurement product functionality, quality, and schedule requirements, supervised by the project’s technical lead.
• Code, verify and document designs, and synthesize and iterate them to timing closure with state‑of‑the‑art EDA tools.

Qualifications

Master’s degree or PhD in Electronics and Chip Design, Information Systems & Signal Processing, Computer Sciences, Applied Physics or equivalent.

Full professional working proficiency in spoken and written English.

Belgian work permit.

It’s a plus if you have experience with any of the following (or you are willing to learn soon):

• Matlab, Python, SystemC.
• The ASIC and/or FPGA design and verification process, e.g.:
  • RTL design entry (VHDL or Verilog).
  • RTL simulation (Mentor, Cadence, ...).
  • Logic synthesis and timing closure (Synopsys, Cadence).
• Linux.
• Git.
• Elementary professional working proficiency in Dutch.

Personal Qualities

• Strong and clear communication, analysis, and problem‑solving skills.
• Affinity with Digital Design, Engineering Mathematics and Digital Signal Processing.
• Proactive programming ability, e.g. in Python.
• Track record as a team player.
• Design creativity and eagerness to learn.
• Self‑reliant, flexible, and can‑do attitude.
• Committed to accurate, high‑quality work delivered on time.

Keysight is an Equal Opportunity Employer.