Front-End ASIC Design Engineer – RTL to GDS

EURAXESS Czech Republic; Heverlee; Sur place; EUR 50 000 - 70 000; Plein temps

Avantages offerts par ce poste

Market-appropriate salary

Fringe benefits

Training through imec.academy

Résumé du poste

EURAXESS Czech Republic is looking for a Digital Front-End Design Engineer based in Heverlee, Belgium. As part of a skilled team, you will handle the RTL-to-GDS flow, ensuring efficiency and high-quality ASIC implementations.

The role requires a master’s degree and experience in ASIC design principles, tackling a variety of design challenges. The position offers a supportive work environment and competitive salary with benefits.

Qualifications

• 0-2 years of experience in ASIC front-end design.
• Master’s degree in a related field required for candidates with no industry experience.
• Proficiency in digital design principles and test strategies.

Responsabilités

• Perform RTL synthesis and optimize timing, area, and power.
• Execute DFT insertion and conduct LEC.
• Generate ATPG patterns and validate design integrity.
• Troubleshoot design issues across the front-end flow.

Connaissances

RTL-to-GDS flow

Synthesis

DFT

LEC

ATPG

Verilog/SystemVerilog

Tcl

Python

Formation

Master’s degree in electrical or computer engineering

Outils

Cadence tools

Synopsys tools

Tessent

Description du poste

EURAXESS Czech Republic is looking for a Digital Front-End Design Engineer based in Heverlee, Belgium. As part of a skilled team, you will handle the RTL-to-GDS flow, ensuring efficiency and high-quality ASIC implementations.

The role requires a master’s degree and experience in ASIC design principles, tackling a variety of design challenges. The position offers a supportive work environment and competitive salary with benefits.