Staff RTL Design Engineer — CPU Core Architect with Equity

IC Resources Recruitment

Town Of Cambridge

On-site

AUD 134,000 - 211,000

Full time

14 days+
Application generator

An application made for this job — a tailored resume and cover letter that speak straight to the posting.

Get past ATS filters

Benefits offered by this job

Annual bonus
Equity / share options
Relocation support
Visa sponsorship
Comprehensive benefits

Job summary

IC Resources Recruitment is seeking a Staff RTL Design Engineer to join a team delivering industry-leading CPU core designs. You will contribute across the full design lifecycle, collaborating with top architects and engineers on demanding projects.

The role requires 6+ years RTL experience, strong Verilog/SystemVerilog/VHDL skills, and a solid software background in C/C++/Python. Relocation and visa sponsorship are available for the right candidate.

Qualifications

  • Bachelor’s or Master’s degree in Computer Science, Computer Engineering, Electrical Engineering, or related field.
  • 6+ years of experience in RTL design.
  • Academic or commercial experience in CPU RTL design.
  • Strong RTL design skills using Verilog, SystemVerilog, or VHDL.
  • Solid software background with C, C++, and Python.
  • Familiarity with DSLs.
  • Experience in test-driven development and unit tests.
  • Attention to detail and high-quality design.

Responsibilities

  • Design and implement industry-leading CPU cores across the full design lifecycle.
  • Collaborate with architects and engineers on technically demanding CPU projects.
  • Contribute to cutting-edge processor development and design verification.

Skills

RTL design
Verilog/SystemVerilog/VHDL
CPU RTL design
C/C++/Python
DSLs
Test-driven development
Attention to detail

Education

Bachelor’s or Master’s degree in CS/EE/CE

Tools

UVM

Job description

IC Resources Recruitment is seeking a Staff RTL Design Engineer to join a team delivering industry-leading CPU core designs. You will contribute across the full design lifecycle, collaborating with top architects and engineers on demanding projects.

The role requires 6+ years RTL experience, strong Verilog/SystemVerilog/VHDL skills, and a solid software background in C/C++/Python. Relocation and visa sponsorship are available for the right candidate.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

Staff RTL Design Engineer
Staff RTL Design Engineer

IC Resources Recruitment • Town Of Cambridge

On-site
AUD 134,000 - 211,000
Annual bonus
Equity / share options
Relocation support
+2
Physical Design Engineer
Physical Design Engineer

IC Resources Recruitment • Town Of Cambridge

On-site
AUD 106,000 - 173,000
Verification Engineer
Verification Engineer

Motion Recruitment • South Australia

On-site
AUD 100,000 - 120,000
Physical Design Engineer: Impactful ASIC/SoC Delivery
Physical Design Engineer: Impactful ASIC/SoC Delivery

IC Resources Recruitment • Town Of Cambridge

On-site
AUD 106,000 - 173,000
FPGA Engineer
FPGA Engineer

Motion Recruitment • South Australia

On-site
AUD 70,000 - 90,000
Senior Staff Runtime Engineer
Senior Staff Runtime Engineer

d-Matrix Australia Pty Ltd • Sydney

On-site
AUD 180,000 - 240,000
Hardware Engineer — High-Speed PCB Design
Hardware Engineer — High-Speed PCB Design

Cyber Assessment Labs • Sydney

On-site
AUD 120,000 - 160,000
Staff Design & Quality Control Engineer
Staff Design & Quality Control Engineer

Avnet • Sydney

On-site
AUD 120,000 - 180,000
Senior Analog Design Engineer – SerDes & DDR
Senior Analog Design Engineer – SerDes & DDR

NovaRays Semi • South Australia

On-site
AUD 140,000 - 210,000
Principal Software Engineer
Principal Software Engineer

CHAOS Industries • City of Melbourne

On-site
AUD 249,000 - 332,000
Stock options (pre-IPO)
Relocation assistance
Annual bonuses
+4