FPGA/ASIC Design Engineer for Space-Grade SoCs

SpaceX; Redmond; On-site; AUD 181,000 - 289,000; Full time

Benefits offered by this job

Stock options and long-term incentives

401(k) retirement plan

Comprehensive medical, vision, dental

Paid vacation and holidays

Shuttle program to Redmond office

Job summary

SpaceX is hiring an FPGA/ASIC Design Engineer to develop next‑gen FPGAs and ASICs for Starlink, working with cross‑functional teams across systems, firmware, and software. You’ll design complex SoCs, optimize power and performance, and participate in full lifecycle from architectural concepts to lab bring‑up.

The role emphasizes collaboration with backend teams and a focus on on-satellite and ground infrastructure deployments to expand Starlink’s global connectivity.

Qualifications

• Bachelor’s degree or higher in a relevant engineering/physics field.
• 1+ years RTL design experience using SystemVerilog, Verilog or VHDL.
• Experience with FPGA/ASIC design flows and verification.

Responsibilities

• Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and integration tasks using Verilog/SystemVerilog.
• Optimize designs for power, performance and area.
• Participate in the full ASIC/FPGA design lifecycle from architecture discussions to microarchitecture and lab bring-up.
• Contribute to continual improvements by building tools to analyze data collected on orbit and in lab.
• Engage in high-level architectural design for test systems to support validation and interoperability.
• Collaborate with software engineers in developing production software for your designs.

Skills

DSP design

RTL design

FPGA/ASIC integration

Python/C/C++

AXI/APB protocols

EDA tools

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics

Master’s in Electrical/Computer Engineering or related field

Tools

HDL simulators (VCS, Questa, IES)

HDL Lint tools (Spyglass)

Xilinx Vivado

Altera Quartus II

Job description

SpaceX is hiring an FPGA/ASIC Design Engineer to develop next‑gen FPGAs and ASICs for Starlink, working with cross‑functional teams across systems, firmware, and software. You’ll design complex SoCs, optimize power and performance, and participate in full lifecycle from architectural concepts to lab bring‑up.

The role emphasizes collaboration with backend teams and a focus on on-satellite and ground infrastructure deployments to expand Starlink’s global connectivity.