Senior Firmware/RTL Engineer

Atto Devices Pty; Sydney; On-site; AUD 150,000 - 210,000; Full time

Job summary

Atto Devices Pty in Sydney seeks a Senior Firmware/RTL Engineer to lead FPGA/ASIC core development for phased-array systems, including architecting the antenna controller FPGA and verified hardware.

You will design, verify and test RTL, implement timing closure and interfaces to beamforming chips, and collaborate across software, hardware and systems teams. Experience with Xilinx/Intel toolchains and lab bring-up is essential.

Qualifications

• Significant FPGA RTL development experience across complex designs.
• Proficient in VHDL/Verilog/SystemVerilog with readable, synthesizable RTL.
• Experience writing self-checking testbenches and performing simulations.
• Solid timing closure and multi-clock design understanding.
• Comfort with SPI/I2C/UART interfaces and processor-to-FPGA layouts.
• Hands-on lab bring-up with oscilloscopes and logic analyzers.

Responsibilities

• Own architecture and integration of the antenna controller FPGA from requirements to verified hardware.
• Support design and verification of ASIC cores.
• Write clean, modular RTL meeting timing/resource constraints.
• Define interfaces between processor subsystem, FPGA and beamforming chips.
• Develop self-checking testbenches and automated regression tests.
• Manage FPGA synthesis, timing constraints, and reset-domain crossing.
• Collaborate with software, hardware and systems engineers on interface requirements.
• Create design docs, interface specs, and verification plans.
• Support hardware bring-up and system integration to resolve faults.

Skills

FPGA development

VHDL/Verilog/SystemVerilog

Testbenches & verification

Timing constraints & closure

Interfaces (SPI/I2C/UART)

Lab hardware bring-up

Linux, VCS & scripting

Technical ownership & cross-discipline

Electrical/Computer Eng degree

Education

Bachelor degree in Electrical or Computer Engineering

Tools

Xilinx Vivado

Intel Quartus

Zynq SoC

Git

Jenkins CI/CD

Job description

We are looking for a Senior Firmware/RTL Engineer to lead the development of FPGA and ASIC cores for our phased-array systems.Working closely with the Head of Software, Hardware and Systems Engineering, a significant FPGA controller for our satellite phased array systems. The role combines hands-on RTL design, verification and lab testing with support for the ASIC cores that control our beamforming chips.

WHAT YOU WILL DO

• Own the architecture, implementation and integration of the antenna controller FPGA, from requirements through to verified hardware.
• Support the design and verification of ASIC cores.
• Write clean, modular and maintainable RTL that meets functional, timing and resource requirements.
• Define and implement interfaces between the processor subsystem, FPGA and beamforming chips, including register maps, control sequencing and status reporting.
• Develop self-checking testbenches, simulations and automated regression tests to verify RTL blocks and integrated designs.
• Manage FPGA synthesis, implementation, timing constraints and timing closure, with sound clock and reset-domain crossing practices.
• Work with software, hardware and systems engineers to resolve interface requirements, review designs and make practical implementation trade-offs.
• Create and maintain design documentation, interface specifications, verification plans and test results.
• Support hardware bring-up, lab-based verification and system integration, identifying the causes of faults and resolving them in line with project priorities.

WHAT YOU WILL BRING

• Significant FPGA development experience, including delivery of complex designs using Xilinx or Intel devices and their associated toolchains.
• Strong proficiency in VHDL, Verilog or SystemVerilog, with a disciplined approach to readable, reusable and synthesizable RTL.
• Practical experience developing self-checking testbenches, running simulations and debugging RTL.
• A sound understanding of timing constraints, timing closure, reset design and safe clock-domain crossings in multi-clock systems.
• Experience designing processor-to-FPGA interfaces and implementing control protocols such as SPI, I2C and UART.
• Confidence bringing up and debugging hardware in the lab using embedded logic analysers, oscilloscopes and other test equipment.
• Familiarity with Linux, version control and scripting to automate builds, tests and development workflows.
• Strong technical judgement, clear written and verbal communication, and the ability to take ownership while working across engineering disciplines.
• A bachelor’s degree in Electrical or Computer Engineering, or equivalent industry experience and professional training.

PREFERRED EXPERIENCE

The following experience would be valuable:

• ASIC RTL design or verification, including familiarity with synthesis flows or structured verification methods such as UVM.
• SoC platforms such as Zynq, and embedded software development in C or C++.
• Python, Bash or Tcl scripting, and continuous integration using tools such as Jenkins or GitLab CI/CD.
• High-speed communications interfaces, fixed-point signal processing, phased arrays or wireless communication systems.

WHY JOIN US

This role offers the opportunity to take ownership of a key part of our phased-array systems and see your designs through to working hardware. You will help shape how our processors and beamforming chips work together, with opportunities to contribute to future ASIC designs in advanced process nodes as our technology develops.We value different experiences and perspectives. If you meet many, but not necessarily all, of the criteria and believe you can make a strong contribution, we encourage you to apply.

SECURITY REQUIREMENTS

Due to the nature of the technology developed by Atto Devices and our work in export-controlled sectors, this position may require access to information and technology subject to Australian defence export-control and security requirements. Applicants must be Australian citizens or Australian permanent residents and must be eligible to access the controlled technology required for the role. The successful candidate may also be required to obtain and maintain any security clearances, export-control authorisations or other approvals required for their work.