Senior FPGA/ASIC Firmware Engineer - Phased-Array Systems

Atto Devices Pty; Sydney; On-site; AUD 150,000 - 210,000; Full time

Job summary

Atto Devices Pty in Sydney seeks a Senior Firmware/RTL Engineer to lead FPGA/ASIC core development for phased-array systems, including architecting the antenna controller FPGA and verified hardware.

You will design, verify and test RTL, implement timing closure and interfaces to beamforming chips, and collaborate across software, hardware and systems teams. Experience with Xilinx/Intel toolchains and lab bring-up is essential.

Qualifications

• Significant FPGA RTL development experience across complex designs.
• Proficient in VHDL/Verilog/SystemVerilog with readable, synthesizable RTL.
• Experience writing self-checking testbenches and performing simulations.
• Solid timing closure and multi-clock design understanding.
• Comfort with SPI/I2C/UART interfaces and processor-to-FPGA layouts.
• Hands-on lab bring-up with oscilloscopes and logic analyzers.

Responsibilities

• Own architecture and integration of the antenna controller FPGA from requirements to verified hardware.
• Support design and verification of ASIC cores.
• Write clean, modular RTL meeting timing/resource constraints.
• Define interfaces between processor subsystem, FPGA and beamforming chips.
• Develop self-checking testbenches and automated regression tests.
• Manage FPGA synthesis, timing constraints, and reset-domain crossing.
• Collaborate with software, hardware and systems engineers on interface requirements.
• Create design docs, interface specs, and verification plans.
• Support hardware bring-up and system integration to resolve faults.

Skills

FPGA development

VHDL/Verilog/SystemVerilog

Testbenches & verification

Timing constraints & closure

Interfaces (SPI/I2C/UART)

Lab hardware bring-up

Linux, VCS & scripting

Technical ownership & cross-discipline

Electrical/Computer Eng degree

Education

Bachelor degree in Electrical or Computer Engineering

Tools

Xilinx Vivado

Intel Quartus

Zynq SoC

Git

Jenkins CI/CD

Job description

Atto Devices Pty in Sydney seeks a Senior Firmware/RTL Engineer to lead FPGA/ASIC core development for phased-array systems, including architecting the antenna controller FPGA and verified hardware.

You will design, verify and test RTL, implement timing closure and interfaces to beamforming chips, and collaborate across software, hardware and systems teams. Experience with Xilinx/Intel toolchains and lab bring-up is essential.