Lead ASIC Verification Engineer, Satellite Communications

Amazon Inc.; Redmond; On-site; AUD 264,000 - 357,000; Full time

Job summary

Amazon Kuiper Manufacturing Enterprises LLC is seeking a senior verification engineer to define and implement digital chip SOC verification for high-speed communications in LEO satellite systems. The role centers on building robust verification environments, writing C/C++ tests, and enabling regression automation across FPGA and emulation platforms.

You will collaborate with design and system teams, apply formal verification techniques, and contribute to test benches using UVM, SystemC, and

Qualifications

• Master's degree or Ph.D. in Electrical Engineering or related field.
• 7+ years in verification preferably in communication systems.
• 5+ years in UVM, C/C++ and scripting.

Responsibilities

• Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models.
• Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program.
• Write tests in C/C++ to execute on embedded CPU.
• Develop tests for FPGA and emulation platforms.
• Run formal verification of complex blocks to ensure functional correctness.
• Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM, SystemC and DPI-C.
• Develop a highly automated environment to run regressions that can be used to make builds and maintain organization of the database.

Skills

UVM

C/C++

SystemC

Scripting

Verifications

Education

Master's or Ph.D. in Electrical Engineering

Tools

Matlab

Formal verification techniques

Job description

Amazon Kuiper Manufacturing Enterprises LLC is seeking a senior verification engineer to define and implement digital chip SOC verification for high-speed communications in LEO satellite systems. The role centers on building robust verification environments, writing C/C++ tests, and enabling regression automation across FPGA and emulation platforms.

You will collaborate with design and system teams, apply formal verification techniques, and contribute to test benches using UVM, SystemC, and