Senior Engineer Mixed Signal Layout (f/m/div)

Infineon Technologies AG; Villach; Vor Ort; EUR 75.000 - 110.000; Vollzeit

Zusammenfassung

Infineon Technologies AG in Austria seeks a Senior Engineer Mixed Signal Layout to drive full-custom IC layout from schematic to tape-out for ADC mixed-signal components. You will optimize layout, perform comprehensive verification, and guide a small team to ensure clean signal integrity.

You will manage parasitics, participate in floor planning and integration while collaborating with ADC design engineers. Fluency in English is essential for this global role.

Qualifikationen

• A bachelor's or master's degree in electrical engineering or a comparable field.
• Ideally 5+ years of hands-on experience in CMOS and FinFET semiconductor technologies.
• High proficiency with industry-standard EDA tools (Cadence Virtuoso, Siemens Calibre, etc.).
• Excellent analytical skills to independently debug complex layout and physical verification issues.
• Excellent communication skills to bridge technical gaps across global, multidisciplinary engineering teams.
• The ability to guide, motivate, and coordinate small layout teams during project execution, and to collaborate closely with ADC Design Engineers.
• Fluent in English.

Aufgaben

• Full Custom Layout: Execute full-custom IC and block-level layout from schematic to tape-out for ADC mixed-signal components.
• Layout Optimization: Implement precise matching techniques and isolation strategies to prevent noise coupling in sensitive analog front-ends.
• Physical Verification: Run and debug full-chip physical verifications, including DRC, LVS, ERC, and antenna rule checks.
• Parasitic Management: Analyze and minimize parasitic resistance, capacitance, and inductance to ensure signal and power integrity.
• Top-Level Integration: Perform floor planning, pad-ring assembly, and final chip integration, considering ESD, latch-up, and electromigration (EM) guidelines.
• Leadership & Mentorship: Provide technical leadership during project execution and mentor junior layout engineers within the team.

Kenntnisse

CMOS & FinFET

EDA tools

Analytical skills

English fluency

Ausbildung

Bachelor's or Master's in electrical engineering

Tools

Cadence Virtuoso

Siemens Calibre

Jobbeschreibung

#WeAreIn for jobs that impact everyone's life.

What if your ideas could change the way the world connects, powers up, or thinks? As a Senior Engineer Mixed Signal Layout in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.

Your role

Key responsibilities in your new role

• Full Custom Layout: Execute full-custom IC and block-level layout from schematic to tape-out for ADC mixed-signal components
• Layout Optimization: Implement precise matching techniques and isolation strategies to prevent noise coupling in sensitive analog front-ends
• Physical Verification: Run and debug full-chip physical verifications, including DRC, LVS, ERC, and antenna rule checks
• Parasitic Management: Analyze and minimize parasitic resistance, capacitance, and inductance to ensure signal and power integrity
• Top-Level Integration: Perform floor planning, pad-ring assembly, and final chip integration, considering ESD, latch-up, and electromigration (EM) guidelines
• Leadership & Mentorship: Provide technical leadership during project execution and mentor junior layout engineers within the team

Your profile

Qualifications and skills to help you succeed

• A bachelor's or master's degree in electrical engineering or a comparable field
• Ideally 5+ years of hands-on experience in CMOS and FinFET semiconductor technologies
• High proficiency with industry-standard EDA tools (Cadence Virtuoso, Siemens Calibre, etc.)
• Excellent analytical skills to independently debug complex layout and physical verification issues
• Excellent communication skills to bridge technical gaps across global, multidisciplinary engineering teams
• The ability to guide, motivate, and coordinate small layout teams during project execution, and to collaborate closely with ADC Design Engineers
• Fluent in English

This position is initially limited to a period of 2 years. We offer competitive salaries and additional benefits based on your performance, experience and qualifications. The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group F-G (https://www.feei.at/leistungen/informations-service/mindestlohne-und-gehalter). The monthly salary is paid 14 times p.a. We offer a higher compensation depending on your expertise and skills.

#WeAreIn for driving decarbonization and digitalization.

As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in?

We are on a journey to create the best Infineon for everyone.

We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity.