Senior Digital Verification Architect — UVM/SoC

NXP Semiconductors; Gratkorn; Vor Ort; EUR 85.000 - 120.000; Vollzeit

Benefits dieser Stelle

Home office

Flexible working time

Meal benefits

Zusammenfassung

NXP Semiconductors in Gratkorn, Austria is seeking a Senior Verification Engineer to own verification of submodules and verification IPs across integration levels. You will review requirements and collaborate with subsystem architects to define a coherent verification strategy.

The role requires 8+ years in digital design and verification, strong SystemVerilog/UVM expertise, and experience with testbench development and formal verification. On-site position with competitive benefits.

Qualifikationen

• Master or PhD in Electrical/Electronic Engineering or Computer Science or equivalent.
• At least eight years of proven professional experience in Digital Design and Verification.
• SystemVerilog and UVM Methodology training certifications from EDA vendors.
• Familiarity with ASIC/SoC design flow and process.
• Advanced knowledge of Verilog and SystemVerilog languages (VHDL a plus).
• Proven experience in testbench design and development using UVM.
• High proficiency in Metric Driven Verification concepts, functional and code coverage.
• High proficiency in directed and constrained random methodologies.
• Advanced knowledge of formal verification methodologies and assertions.
• Proficiency with languages used for testcases development: bash/tcsh, tcl, Python and C.
• Experience with Centralized Version Control Systems (e.g. SVN, GIT, Clearcase).
• Comfortable working in a collaborative and technically demanding team/group.
• Very good spoken and written English skills.

Aufgaben

• Take ownership and responsibility of verification of one or more submodules, including verification IPs and testbenches at different levels of integration.
• Review, understand and discuss subsystem/submodules requirements and design specifications at each new functional or technology increment.
• Collaborate with the subsystem architect and discipline leads in defining a unified verification strategy.
• Collaborate with DV team to break down strategy into activities and tasks with effort and priorities.
• Define and document metrics and the methodology to assess completion of verification.
• Support the definition and specifications of testbench components.
• Track and document verification activity with respect to process and requirements.
• Create or update verification specs and reports at project phase reviews.
• Interact with HW and SW designers, system engineers for issue analysis and resolution.
• Contribute to DV process maintenance and documentation, and to methodology improvements.
• Keep updated with latest verification methodology and tools via courses/seminars/webinars.

Kenntnisse

SystemVerilog

UVM

Verilog

VHDL

Python

C

Shell scripting

Git

SVN

Clearcase

Ausbildung

Master or PhD in Electrical/Electronic Engineering or Computer Science

Tools

Git

SVN

Clearcase

Jobbeschreibung

NXP Semiconductors in Gratkorn, Austria is seeking a Senior Verification Engineer to own verification of submodules and verification IPs across integration levels. You will review requirements and collaborate with subsystem architects to define a coherent verification strategy.

The role requires 8+ years in digital design and verification, strong SystemVerilog/UVM expertise, and experience with testbench development and formal verification. On-site position with competitive benefits.