Senior High-Speed Analog Layout Architect

Celero Communications, Inc.; Córdoba; Presencial; ARS 180.802.000 - 271.203.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Foundational startup role

International collaboration

Growth opportunities

Challenging projects

Descripción de la vacante

Celero Communications, Inc. in Argentina seeks Senior/Principal High-Speed Analog Layout Design Engineer to drive layout of ADCs, DACs, PLLs, and other high-performance blocks, interfacing with circuit designers and CAD/PDK teams.

This hands-on role involves leading floor planning, routing, LVS/DRC checks, and contributing to chip-level planning. Mentoring junior engineers across time zones and pushing for first-pass silicon success.

Formación

• 10+ years in analog/mixed-signal layout in CMOS/FinFET technologies.
• Experience with top-level IP layout macros.
• Experience with FinFET nodes (TSMC N3/N5/N7/N16).
• Strong knowledge of LVS/DRC/PERC/ERC and parasitic minimization.

Responsabilidades

• Lead and own the physical layout design of complex analog/mixed-signal macros from floor planning through final verification.
• Collaborate with schematic designers for optimal layout solutions.
• Mentor junior layout engineers across time zones and enforce best practices.
• Perform and debug LVS, DRC, PERC, ERC, and other signoff checks.
• Contribute to chip-level planning, floor planning, power grid, and routing.
• Participate in layout design reviews and drive quality and schedule.
• Support automation through scripting (SKILL, TCL, Python).

Conocimientos

Analog layout

Leadership

Mentoring

Schematic collaboration

Device matching

High-speed design

Documentation

Herramientas

Cadence Virtuoso

Calibre

Pegasus

Descripción del empleo

Celero Communications, Inc. in Argentina seeks Senior/Principal High-Speed Analog Layout Design Engineer to drive layout of ADCs, DACs, PLLs, and other high-performance blocks, interfacing with circuit designers and CAD/PDK teams.

This hands-on role involves leading floor planning, routing, LVS/DRC checks, and contributing to chip-level planning. Mentoring junior engineers across time zones and pushing for first-pass silicon success.