Lead High-Speed Analog Layout Engineer — Mentor & Drive IP

Emploive; Córdoba; Híbrido; ARS 1.200.000 - 2.400.000; Jornada completa

Descripción de la vacante

Celero Communications, a fast-growing semiconductor startup, is seeking a High-Speed Analog Layout Design Engineer to drive layout development of analog/mixed-signal IP blocks such as ADCs, DACs, PLLs for our optical communication systems.

You will mentor junior layout engineers across time zones, work with circuit designers and CAD/PDK teams, and ensure first-pass silicon success through thorough LVS/DRC checks and robust floorplanning.

Formación

• 1+ years of hands-on analog/mixed-signal layout in CMOS/FinFET tech.
• Top-level IP layout macros experience and handoff readiness.
• Leadership in owning major IP layout macros or full-chip layout at FinFET nodes (TSMC preferred).

Responsabilidades

• Lead physical layout design of complex analog/mixed-signal macros from floor planning to verification.
• Collaborate with schematic designers for optimal layout considering performance, matching, symmetry, and reliability.
• Mentor junior layout engineers across multiple time zones, enforcing best practices in layout and verification.
• Perform LVS, DRC, PERC, ERC, and other checks using Pegasus, Calibre, and related tools.
• Contribute to chip-level planning including floor planning, block integration, power/ground grid design, and routing.
• Participate in layout reviews and provide technical leadership for quality and schedule adherence.

Conocimientos

Analog/mixed-signal layout

Leadership

Mentoring

Cross-functional collaboration

Documentation

Herramientas

Cadence Virtuoso

Calibre

Pegasus

Descripción del empleo

Celero Communications, a fast-growing semiconductor startup, is seeking a High-Speed Analog Layout Design Engineer to drive layout development of analog/mixed-signal IP blocks such as ADCs, DACs, PLLs for our optical communication systems.

You will mentor junior layout engineers across time zones, work with circuit designers and CAD/PDK teams, and ensure first-pass silicon success through thorough LVS/DRC checks and robust floorplanning.