Senior Analog Layout Architect – High‑Speed IP

Celero Communications; Córdoba; Presencial; ARS 2.400.000 - 4.200.000; Jornada completa

Descripción de la vacante

Celero Communications is seeking a Senior Analog Layout Design Engineer to lead the physical layout of complex analog/mixed-signal blocks for innovative optical communication systems. You will collaborate with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success.

You will mentor junior engineers, drive layout quality and verification, and contribute to top-level planning and automation efforts in a fast-paced, globally distributed environment.

Formación

• Minimum 3+ years of hands-on analog/mixed-signal layout design experience in advanced CMOS/FinFET technologies.
• Proven track record of top-level integration IP layout macros and preparing IPs for handoff to Physical Design.
• Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes (TSMC preferred).
• At least 1 year of experience with TSMC FinFET process nodes (N3, N5, N7, or N16).
• Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance.
• Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization.

Responsabilidades

• Lead and own the physical layout design of complex analog/mixed-signal macros (e.g., ADCs, DACs, PLLs), from floor planning through final verification
• Collaborate closely with schematic designers to create optimal layout solutions considering performance, matching, symmetry, and reliability
• Mentor and guide junior layout engineers/contractors across multiple time zones, enforcing best practices in layout design and verification
• Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks using industry-standard tools (Pegasus, Calibre, etc.)
• Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing
• Participate in layout design reviews and provide technical leadership for layout quality, verification completeness, and schedule adherence
• Support automation initiatives through scripting and tool customization (SKILL, TCL, Python is a plus)

Conocimientos

Leadership

Mentoring

Cross-functional collaboration

Documentation & communication

Scripting (Python/TCL)

Herramientas

Cadence Virtuoso

Calibre

Pegasus

Layout verification tools

Descripción del empleo

Celero Communications is seeking a Senior Analog Layout Design Engineer to lead the physical layout of complex analog/mixed-signal blocks for innovative optical communication systems. You will collaborate with circuit designers, CAD/PDK teams, and other layout engineers to ensure first-pass silicon success.

You will mentor junior engineers, drive layout quality and verification, and contribute to top-level planning and automation efforts in a fast-paced, globally distributed environment.