Senior SoC Emulation Engineer

Evollabs; Dubai; On-site; AED 420,000 - 600,000; Full time

Job summary

Evollabs is seeking a senior position in Dubai to own the development and bring-up of hardware emulation environments for next-generation AI/HPC SoCs. You will enable full-system validation, accelerate hardware/software integration, and support early firmware and software development before silicon is available.

Collaborating with RTL, verification, firmware, and software teams, you will drive pre-silicon validation, optimize emulation performance, and address complex system-level issues across

Qualifications

• 7+ years in ASIC/SoC design, verification, or emulation.
• Hands-on hardware emulation experience.
• Ownership of subsystem or full-SoC emulation bring-up from RTL compilation to execution and debugging.
• Strong knowledge of Verilog/SystemVerilog, SoC architecture, and AMB protocols (AXI/APB).
• Experience with emulation-compatible test environments, BFMs, transactors, and system-level debugging.
• Good understanding of CPU subsystems, NoC/interconnect, DMA, memory systems, clocks, resets, and interrupts.
• Proficiency in C/C++, Python, Tcl/Bash, Linux, and automation workflows.
• Experience supporting firmware-driven verification and hardware/software integration.

Responsibilities

• Own SoC emulation: Build, integrate, and maintain subsystem and full-chip emulation environments using commercial hardware emulation platforms.
• RTL bring-up and optimization: Compile, partition, map, and optimize RTL designs for emulation, resolving compatibility, performance, and integration issues.
• Verification acceleration: Adapt UVM environments, develop BFMs and transactors, and enable hardware-accelerated verification.
• HW/SW co-verification: Enable processor boot, firmware execution, driver development, and software-driven system validation.
• System-level debugging: Investigate complex issues across CPU, NoC, DMA, memory, high-speed interfaces, and peripheral subsystems.
• Automation and infrastructure: Develop reliable emulation build flows, regressions, CI integration, and debugging automation.
• Integration and collaboration: Support third-party IP integration, maintain reproducible environments, and drive issues to resolution across engineering teams.

Skills

ASIC/SoC design

Emulation platforms

RTL bring-up

Verilog/SystemVerilog

C/C++ scripting

Tools

Cadence Palladium

Synopsys ZeBu

Siemens Veloce

Job description

Own the development and bring-up of hardware emulation environments for next-generation AI/HPC SoCs. You'll enable full-system validation, acceleratehardware/software integration, and support early firmware and softwaredevelopment before silicon is available. Working across RTL, verification, andsoftware teams, you'll help identify complex system-level issues early and drive ourAI silicon toward successful tape-out.

Responsibilities

• Own SoC emulation: Build, integrate, and maintain subsystem and full-chipemulation environments using commercial hardware emulation platforms.
• RTL bring-up and optimization: Compile, partition, map, and optimize RTL designsfor emulation, resolving compatibility, performance, and integration issues.
• Verification acceleration: Adapt UVM environments, develop BFMs andtransactors, and enable hardware-accelerated verification.
• HW/SW co-verification: Enable processor boot, firmware execution, driverdevelopment, and software-driven system validation.
• System-level debugging: Investigate complexissues across CPU, NoC, DMA,memory, high-speed interfaces, and peripheral subsystems.
• Automation and infrastructure: Develop reliable emulation build flows,regressions, CI integration, and debugging automation.
• Integration and collaboration: Support third-party IP integration, maintainreproducible environments, and drive issues to resolution across engineeringteams.

You'll Collaborate WithSoC architects, RTL designers, Functional Verification engineers, Firmware and Software teams, and EDA/CAD engineers to enable early system validation, improveemulation performance, and accelerate pre-silicon development.

Minimum Qualifications

• 7+ years of ASIC/SoC design, verification, or emulation experience, withsubstantial hands-on hardware emulation experience.
• Proven experience with commercial hardware emulation platforms such asCadence Palladium, Synopsys ZeBu, or Siemens Veloce.
• Demonstrated ownership of subsystem or full-SoC emulation bring-up, from RTLcompilation and mapping to execution and debugging.
• Strong knowledge of Verilog/SystemVerilog, SoC architecture, and AMBprotocols (AXI/APB).
• Experience with emulation-compatible test environments, BFMs, transactors, andsystem-level debugging.
• Good understanding of CPU subsystems, NoC/interconnect, DMA, memorysystems, clocks, resets, and interrupts.
• Proficiency in C/C++, Python, Tcl/Bash, Linux, and automation workflows.
• Experience supporting firmware-driven verification and hardware/softwareintegration.

Preferred (Nice-to-Haves)

• Experience with UVM acceleration, SCE-MI, DPI-C, and transaction-basedemulation.
• Experience with RISC-V/ARM processors, JTAG, boot flows, and embeddedfirmware.
• Exposure toAI accelerators, HPC SoCs, PCIe, Ethernet, CXL, UCIe, or advancedmemory architectures.
• Experience with FPGA prototyping, virtual platforms, or hybridsimulation/emulation environments.
• Experience with multi-die SoCs, low-power validation, or post-silicon bring-up.

Evollabs Tech FZ-LLCDIC-Bldg. 05-118,Dubai Internet CityUnited Arab Emirates