Network CCL Engineer Gateworth Group On-site Fast Track available

HireHouse; Dubai; On-site; AED 350,000 - 500,000; Full time

Benefits offered by this job

Bonus

Benefits

Job summary

Gateworth Group in Dubai, United Arab Emirates, seeks a Network CCL Engineer to advance collective communication for accelerator-based AI platforms. You will develop primitives and runtimes, enabling robust multi-device workflows across PCIe, RDMA, and custom fabrics.

The role emphasizes low-level performance and close collaboration with hardware, runtime, and distributed systems teams. The ideal candidate brings 5+ years in distributed systems or accelerator development, strong C/C++ and Python

Qualifications

• 5+ years in distributed systems, runtime engineering, networking or accelerator-level development.
• Strong C/C++ and Python programming experience.
• Solid understanding of collective communication operations (AllReduce, ReduceScatter, AllGather, AllToAll, Broadcast, Send/Recv, Barrier).
• Familiarity with libraries such as NCCL, RCCL, oneCCL, MPI, UCX or libfabric.
• A good understanding of GPU/NPU memory behaviour, memory registration, peer-to-peer transfers and heterogeneous device communication.
• Experience with runtime concepts including queues, streams, events, command submission, synchronization and memory management.
• Understanding of hardware-software interaction: DMA engines, device memory, interrupts, doorbells, fences and completion signalling.
• Knowledge of high-performance networking technologies (InfiniBand, RoCE).
• Experience with distributed training frameworks or custom communication backends is a bonus.
• Exposure to communication optimisation for LLM workloads (tensor parallelism, MoE, KV-cache movement) would be advantageous.
• Experience integrating communication layers with modern distributed inference frameworks would be helpful.

Responsibilities

• Develop collective communication primitives for accelerator-based systems.
• Build communication support for multi-device and rack-level inference environments.
• Design heterogeneous communication paths across accelerator and GPU devices.
• Create the runtime components for device discovery, rank management, topology awareness, queues, streams, events and synchronization.
• Integrate transport mechanisms across PCIe, RDMA-based networking, custom fabrics and device-to-device communication.
• Collaborate with hardware, runtime, compiler and distributed systems teams on scalable communication solutions.
• Diagnose and optimise communication bottlenecks including bandwidth, latency, congestion and synchronization overhead.

Skills

Distributed systems

C/C++

Python

Memory management

GPU memory

Device communication

Runtime engineering

Tools

NCCL

RCCL

oneCCL

MPI

UCX

libfabric

Job description

Position: Network CCL Engineer

Compensation: Competitive Salary + Bonus + Benefits

Location: Dubai, United Arab Emirates

Overview

Gateworth Group is supporting a high‑growth technology business that is building advanced accelerator hardware and large‑scale AI infrastructure, and they’re looking for a Network CCL Engineer who can operate deep in the performance layer. This role focuses on collective communication, accelerator runtime, heterogeneous device communication and distributed AI workloads. It suits someone who enjoys low‑level engineering, understands how accelerators behave at scale, and can design communication paths that perform across multi‑chip and multi‑rack environments. You’ll work closely with hardware, runtime and distributed systems teams to build communication foundations for next‑generation AI platforms.

Main Responsibilities

• Develop collective communication primitives for accelerator‑based systems.
• Build communication support for multi‑device and rack‑level inference environments.
• Design heterogeneous communication paths across accelerator and GPU devices.
• Create the runtime components for device discovery, rank management, topology awareness, queues, streams, events and synchronization.
• Integrate transport mechanisms across PCIe, RDMA‑based networking, custom fabrics and device‑to‑device communication.
• Collaborate with hardware, runtime, compiler and distributed systems teams on scalable communication solutions.
• Diagnose and optimise communication bottlenecks including bandwidth, latency, congestion and synchronization overhead.

Qualifications

• 5+ years in distributed systems, runtime engineering, networking or accelerator‑level development.
• Strong C/C++ and Python programming experience.
• Solid understanding of collective communication operations (AllReduce, ReduceScatter, AllGather, AllToAll, Broadcast, Send/Recv, Barrier).
• Familiarity with libraries such as NCCL, RCCL, oneCCL, MPI, UCX or libfabric.
• A good understanding of GPU/NPU memory behaviour, memory registration, peer‑to‑peer transfers and heterogeneous device communication.
• Experience with runtime concepts including queues, streams, events, command submission, synchronization and memory management.
• Understanding of hardware‑software interaction: DMA engines, device memory, interrupts, doorbells, fences and completion signalling.
• Knowledge of high‑performance networking technologies (InfiniBand, RoCE).
• Experience with distributed training frameworks or custom communication backends is a bonus.
• Exposure to communication optimisation for LLM workloads (tensor parallelism, MoE, KV‑cache movement) would be advantageous.
• Experience integrating communication layers with modern distributed inference frameworks would be helpful.