Lead FPGA Architect — High-Speed SerDes & T&M

Remotedxb; Dubai; On-site; AED 300,000 - 460,000; Full time

Job summary

Luxoft in Dubai is seeking an expert FPGA Architect to own end-to-end FPGA development for state-of-the-art communications products. You will drive architecture, IP selection, timing closure, and DFX while mentoring a team of FPGA engineers.

Qualifications include a BS/MS in Electrical/Computer Engineering and 12–15 years of relevant experience, with deep HDL expertise and track record in multi-Gbps SerDes/transceiver designs. Fluency in English is required.

Qualifications

• Bachelor or Master in Electrical or Computer Engineering with strong HDL background.
• Proven experience in architecting and delivering multi-Gbps FPGA designs.
• Experience with high-speed serial interfaces and Ethernet link-layer debugging.

Responsibilities

• Own FPGA architecture for state-of-the-art communications products.
• Define end-to-end FPGA architecture and IP make/buy tradeoffs.
• Oversee floorplanning and timing closure for multi-Gbps designs.
• Implement DFX approaches using HDL languages.
• Serve as escalation point for FPGA design and debugging issues.
• Mentor fellow FPGA engineers and drive root-cause analysis.
• Lead silicon/board bring-up debugging and issue resolution.

Skills

FPGA architecture

Verilog/SystemVerilog/VHDL

Timing closure

DFX for FPGA

High-speed transceivers

Hard IP & PLLs

Verifications (UVM/Cocotb)

Git/version control

Debugging silicon/board bring-up

PCIe & multi-Gbps design

Open verification methodologies

AI-assisted design tools

Education

BS or MS in Electrical or Computer Engineering

Tools

AMD/Altera FPGA toolchains

Siemens Questa

Aldec Riviera

Open verification flow (cocotb)

Job description

Luxoft in Dubai is seeking an expert FPGA Architect to own end-to-end FPGA development for state-of-the-art communications products. You will drive architecture, IP selection, timing closure, and DFX while mentoring a team of FPGA engineers.

Qualifications include a BS/MS in Electrical/Computer Engineering and 12–15 years of relevant experience, with deep HDL expertise and track record in multi-Gbps SerDes/transceiver designs. Fluency in English is required.