VLSI Validation Lead — Silicon Bring-Up & RTL Debug

Wipro; Sunnyvale (CA); On-site; USD 80,000 - 150,000; Full time

Benefits offered by this job

Medical & dental benefits

Disability insurance

Paid time off

Job summary

Wipro in Sunnyvale, California, is seeking an experienced silicon validation engineer focused on display and SOC verification. You will validate display SOC, mixed-signal SOC, and IP, and define validation strategies aligned with RTL, architecture, and FW.

You will develop validation infrastructure, code in C/C++ and Python (Zebu), FPGA (HAPS), and work on bring-up, workload enablement, SW stack validation, and power/performance characterization.

Qualifications

• Experience: 5-8 years in silicon validation.
• Mandatory skills: PSV, RTL, Debugging, ARM SOC.
• Display domain focus is important even if ML coprocesor background is not required.

Responsibilities

• Execute bring-up/debug, workload enablement, and SW stack validation.
• Perform performance and power characterization.
• Create automated data collection flows and convert large datasets into executive summaries.
• Track test coverage, document bugs, drive cross-functional debug, and verify silicon fixes.
• Collaborate with factory test teams to align validation and production characterization strategies.

Skills

PSV

RTL

Debugging

ARM SOC

Tools

C/C++

Python

Job description

Wipro in Sunnyvale, California, is seeking an experienced silicon validation engineer focused on display and SOC verification. You will validate display SOC, mixed-signal SOC, and IP, and define validation strategies aligned with RTL, architecture, and FW.

You will develop validation infrastructure, code in C/C++ and Python (Zebu), FPGA (HAPS), and work on bring-up, workload enablement, SW stack validation, and power/performance characterization.