Verification Engineer: Formal Verification & Automation

ManpowerGroup Global, Inc.; Austin (TX); On-site; USD 110,000 - 160,000; Full time

Job summary

ManpowerGroup Global, Inc. in Austin, TX is seeking a Verification Engineer to join the Design Verification Department, supporting innovative projects and collaborative teams.

You will perform formal verification with VC Formal or Jasper Gold, develop SystemVerilog Assertions, apply FPV and coverage analyses, and automate flows using TCL, Python, or Perl while coordinating with design and verification colleagues.

Qualifications

• Hands-on experience with VC Formal and/or Jasper Gold tools.
• Strong proficiency in SystemVerilog Assertions and formal property specification.
• Experience with FPV, connectivity checking, register verification, and coverage analysis.
• Familiarity with scripting languages such as TCL, Python, or Perl for flow automation.
• Extensive experience in design verification with a focus on formal verification methodologies.

Responsibilities

• Perform formal verification using VC Formal (Synopsys) and/or Jasper Gold (Cadence) to ensure design correctness.
• Develop and maintain System Verilog Assertions (SVA) and formal property specifications for complex hardware modules.
• Apply formal verification applications such as FPV, connectivity checking, register verification, and coverage analysis to validate design integrity.
• Automate verification flows using scripting languages like TCL, Python, or Perl to improve efficiency and accuracy.
• Collaborate with design and verification teams to identify issues early and implement effective solutions.

Skills

SVA (SystemVerilog Assertions)

Formal verification

Analytical problem solving

Communication skills

Tools

VC Formal (Synopsys)

Jasper Gold (Cadence)

TCL

Python

Perl

FPV

Job description

ManpowerGroup Global, Inc. in Austin, TX is seeking a Verification Engineer to join the Design Verification Department, supporting innovative projects and collaborative teams.

You will perform formal verification with VC Formal or Jasper Gold, develop SystemVerilog Assertions, apply FPV and coverage analyses, and automate flows using TCL, Python, or Perl while coordinating with design and verification colleagues.