TPU SoC Design Engineer, Google Cloud

Google; United States; On-site; USD 116,000 - 166,000; Full time

Benefits offered by this job

Bonus target

Equity

Benefits

Job summary

Google is seeking a TPU SoC Design Engineer in Sunnyvale, CA to help shape the future of AI/ML hardware acceleration. You will work on TPU architecture and integration within AI/ML driven systems, delivering custom silicon for data-center workloads.

The role focuses on SoC RTL design, top-level architecture, and collaboration with Verification, Physical Design, and Firmware teams. You will write SystemVerilog RTL, optimize for timing and power, and contribute to scalable tooling for ASIC

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 2 years of experience in ASIC RTL design using SystemVerilog or Verilog.
• Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.
• Experience with digital design, including synchronous and asynchronous logic, state machines, and bus protocols.

Responsibilities

• Define and document the microarchitecture for digital designs within the TPU.
• Write RTL code in SystemVerilog, focusing on performance and power efficiency.
• Collaborate with Verification to develop test plans, debug RTL, and ensure functional correctness.
• Work with Physical Design to meet timing, area, power, and manufacturability goals.
• Contribute to the development and enhancement of design tools, flows, and methodologies.

Skills

ASIC RTL design

SystemVerilog

EDA tools

Digital design

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Tools

Verdi

VCS

Job description

TPU SoC Design Engineer, Google Cloud

Location : Sunnyvale, CA, USA

Experience Level : Early

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.
• 2 years of experience in ASIC RTL design using SystemVerilog or Verilog.
• Experience with industry-standard EDA tools for simulation, synthesis, and power analysis.
• Experience with digital design, including synchronous and asynchronous logic, state machines, and bus protocols.

Preferred Qualifications

• Master's degree or PhD in Electrical Engineering or Computer Engineering, with an emphasis on computer architecture.
• 5 years of experience with RTL coding using Verilog/SystemVerilog.
• Experience in scripting (e.g., Python, Tcl, or Perl) and debugging with tools like Verdi or VCS.
• Experience with SoC implementation standards and interfaces (e.g., AXI).
• Experience architecting RTL solutions employing software-based construction, instantiation, customization, and generation of RTL.
• Experience with CDC, UPF, RDC, RTL Linting, and LEC.

About the Job

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will be working on SoC-level RTL design for our data center accelerators. You will work on top-level RTL, architecture, design and implementation of global communication buses, and integration of complex ASIC designs. This is a cross-functional and central role that will require interactions with numerous ASIC development teams. You will own deliverables to the cross-functional teams (e.g., Physical Design, Verification, Validation, Firmware) at various project milestones. You will also be directly involved in defining and creating methodologies that enable an efficient design environment for all ASIC engineers.

You will be a key contributor to the development of Google's AI accelerators. You will create innovative and efficient hardware solutions. You will have the opportunity to work on technical problems at the forefront of AI hardware, working in a dynamic and collaborative environment.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability, and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware, our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US Pay Range

$116,000 - $166,000 (USD) + 15% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Define and document the microarchitecture for digital designs within the TPU.
• Write performant, power-efficient Register Transfer Level (RTL) code, primarily in SystemVerilog.
• Collaborate with the Verification team to develop test plans, debug RTL, and ensure functional correctness.
• Work with the Physical Design team to meet timing, area, power, and manufacturability requirements.
• Contribute to the development and enhancement of design tools, flows, and methodologies.

Additional Information

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Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.

If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.