Senior Staff Performance Codesign Engineer, TPU

Google; Sunnyvale (CA); On-site; USD 240,000 - 333,000; Full time

Job summary

Google Sunnyvale, CA invites a Senior Staff Performance Codesign Engineer to shape TPU hardware and software for world-class AI/ML workloads. You will drive architecture decisions, verify complex digital designs, and align research with production systems powering billions of user-facing services.

The role emphasizes cross‑functional leadership, performance modeling, and scalable ML pipelines, with opportunities to influence multi‑generational hardware solutions and next‑gen accelerators.

Qualifications

• Bachelor's degree or equivalent practical experience in a related field.
• 12 years of experience in computer/chip architecture or hardware-software co-design.
• Experience with performance modeling, simulation or system analysis.

Responsibilities

• Define and drive the technical roadmap and architecture for the hardware/software stack for ML training and serving.
• Act as the technical liaison between advanced research, software, and hardware teams to maximize scaling and efficiency.
• Architect and oversee next‑generation configurable simulation frameworks and cycle‑accurate performance models.
• Advocate system‑level performance analysis across distributed ML systems and optimize compute/memory/interconnect requirements.
• Manage cross‑functional partnerships to influence strategy and production transitions.

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience

12 years of experience in computer architecture, chip architecture, or hardware-software co-design

Experience developing systems for performance modeling, simulation, or system analysis

Job description

Senior Staff Performance Codesign Engineer, TPU

Google

Sunnyvale, CA, USA

Advanced

Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders; deep expertise in domain.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 12 years of experience in computer architecture, chip architecture, or hardware-software co-design.
• Experience developing systems for performance modeling, simulation, or system analysis.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience as a lead architect driving multi-generational hardware solutions or performance optimizations for massive-scale ML training and inference.
• Experience with deep learning frameworks (e.g., PyTorch, TensorFlow) and their underlying execution models.
• Knowledge of semiconductor trajectories, including process, memory, interconnects, and packaging.
• Understanding of ML trends, business drivers, and the software ecosystem.
• Ability to engage and align stakeholders, hardware designers, and the global ML research community.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a Senior Staff Co-Design Engineer on the TPU Chip Architecture team, you will bridge the gap between model architecture innovation and next‑generation hardware design. Operating at the intersection of AI research and infrastructure engineering, you will define the long‑term strategic outlook and architectural roadmap for our future machine learning training and serving capabilities. You will advocate the integration of foundational ML research—such as massive‑scale frontier models—with advanced custom silicon architectures to deliver industry‑defining, high‑performance, and power‑efficient accelerators.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We’re the driving force behind Google’s groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job‑related skills, experience, and relevant education or training.

US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits

Learn more about benefits at Google.

Responsibilities

• Define and drive the technical roadmap and architecture for the hardware/software stack, ensuring unparalleled performance for the training and serving of large ML models.
• Act as the technical liaison between advanced research, software, and hardware teams, steering model architecture innovation to maximize scaling, quality, and hardware efficiency.
• Architect and oversee the development of next‑generation configurable simulation frameworks and cycle‑accurate performance models, setting the standard for how the organization evaluates complex micro‑architectural decisions.
• Advocate system‑level performance analysis across highly distributed ML systems, innovating new methodologies to balance compute, memory bandwidth, and inter‑chip network requirements.
• Manage cross‑functional partnerships across hardware engineering, compiler development, and ML research to influence broad organizational strategy and transition paradigm‑shifting concepts into production.

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