Top-Level Static Timing Analysis And Timing Closure Engineer

Sivaltech; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Sivaltech is seeking an experienced ASIC/SoC timing closure specialist for top-level signoff in a cutting-edge environment. Your expertise will drive timing closure, signoff accuracy, and ECO validation for complex SoCs in a fast-paced semiconductor team.

• Proficient in PrimeTime/Tempus, CMA, and signoff methodologies. • Strong scripting in Tcl and Python to automate flows. • Collaboration with design, verification, and tapeout teams for successful silicon.

Qualifications

• Experience in ASIC/SoC top-level timing closure and signoff required.
• Strong knowledge of STA/Timing Closure methodologies and tools.

Skills

Full-chip / Top-level STA and Timing |

Post-layout timing signoff

PrimeTime and/or Tempus

MMMC, SDC, Setup & Hold closure

SI/Crosstalk, OCV, AOCV/POCV

ECO implementation

Tcl and Python scripting

Job description

Key Skills:

• Full-chip / Top-level STA and Timing Closure
• Post-layout timing signoff
• PrimeTime and/or Tempus
• MMMC, SDC, Setup & Hold closure
• SI/Crosstalk, OCV, AOCV/POCV
• ECO implementation
• Tcl and Python scripting

If you have strong experience in ASIC/SoC top-level timing closure and signoff, we would like to hear from you!

Interested candidates, please share your updated resume.

• #Hiring #Sivaltech #STA #TimingClosure #ASIC #SoC #PrimeTime #Tempus #SemiconductorJobs