Test Engineer – ATE

Riana Technologies; San Jose (CA); On-site; USD 90,000 - 130,000; Full time

Job summary

Riana Technologies in San Jose, CA is seeking a Test Engineer – ATE / Bench to own test program development for Digital, PMIC, RF and Mixed Signal ICs.

You will work with design engineers on first-silicon debug, device characterization, and production release activities across our San Jose and Dallas locations.

This role requires 3–7 years of experience and a degree in Electronics / Electrical Engineering; hands-on Advantest 93K ATE SMT8 experience is required.

Qualifications

• Degree in Electronics / Electrical Engineering.
• 3–7 years of relevant Test Engineering experience preferred.
• Hands-on Advantest 93K ATE SMT8 experience required.
• Experience using bench instrumentation for IC characterization.
• Solid knowledge of analog and digital electronics.
• Strong analytical and problem-solving skills; good communication.

Responsibilities

• Develop test programs for Digital, PMIC, RF & Mixed Signal on Bench and/or ATE (Advantest 93K – SmarTest 7, SmarTest 8).
• Partner with design engineers on first silicon debug, device characterization, test program bring-up, and production release.
• Debug digital vectors (JTAG/SCAN/ATPG/Functional/Mbist) and characterize devices across PVT.
• Characterize RF, PMIC, or Mixed Signal IP (ADC, DAC, PLL, etc.).
• Support test program hand-off, production release, yield improvement, and test time reduction initiatives.
• Collaborate with Product, Design, Quality, and Foundry Eng teams.

Skills

Test program dev

Digital

PMIC

RF

Mixed-Signal

Education

Electronics/Electrical Eng. degree

Tools

Advantest 93K ATE SMT8

Job description

Job Title: Test Engineer – ATE / Bench (Digital, PMIC, RF & Mixed Signal)

3055 Orchard Drive, Suite 150, San Jose, CA 95134

About the Role

As a Test Engineer, you'll own test program development and debug for complex ICs spanning Digital, PMIC, RF, and Mixed Signal categories. You'll work at the intersection of silicon bring-up, device characterization, and production test — collaborating directly with design engineers to resolve first-silicon issues and drive programs to volume production.

Skills & Description:

Test program development for Digital, PMIC, RF & Mixed Signal products on Bench and (or) ATE primarily on Advantest 93k - SmarTest 7, SmarTest 8. Work closely with design engineers on first silicon debug, device characterization, test program bring-up, and production release activities across our San Jose, CA and Dallas, TX locations.

What You'll Do

• Develop test programs for Digital, PMIC, RF & Mixed Signal products on Bench and/or ATE (Advantest 93K – SmarTest 7, SmarTest 8)
• Partner with design engineers on first silicon debug, device characterization, test program bring-up, and production release
• Debug digital vectors (JTAG/SCAN/ATPG/Functional/Mbist) and characterize devices across PVT (Process, Voltage, Temperature)
• Characterize RF, PMIC, or Mixed Signal IP (ADC, DAC, PLL, etc.)
• Support test program hand-off, production release, yield improvement, and test time reduction initiatives
• Collaborate closely with Product Engineering, Design Engineering, Quality Engineering, and Foundry Engineering teams

What You Bring

• Degree in Electronics / Electrical Engineering
• 3–7 years of relevant Test Engineering experience preferred
• Hands-on experience with Advantest 93K ATE SMT8 (required)
• Experience using bench instrumentation for IC characterization
• Solid knowledge of analog and digital electronics
• Strong analytical and problem-solving skills with a hands-on lab mindset
• Excellent verbal and written communication skills; able to work independently
• Willingness to be based in San Jose, CA or Dallas, TX