Technical Lead Engineer — Network Validation & Characterization

Meta Careers; Sunnyvale (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

Meta is seeking a senior ASIC validation engineer for its Infrastructure team in Sunnyvale, CA. You will lead hands-on validation and characterization of complex NICs/SoCs from first silicon through high-volume production, focusing on PVT, power delivery, and high-speed interfaces.

You will develop tests and scalable lab automation in Python, work with ODMs and silicon/IP vendors, and apply Linux networking, DPDK, and RDMA knowledge to debug and optimize performance.

Qualifications

• Hands-on validation and characterization of complex ASICs/SoCs is required.
• Experience taking NICs from first silicon through high-volume production.
• Strong ability to read schematics and analyze power delivery networks or high-speed interfaces.
• Proficiency in Python for test development, automation, and data analysis.
• Experience with Linux networking internals and DPDK or verbs.
• Familiarity with ODMs and silicon/IP vendors.

Responsibilities

• Lead pre-silicon validation on emulation platforms, first-silicon bring-up, and post-silicon characterization.
• Develop tests and scalable lab automation for large ASIC fleets.
• Collaborate with ODMs and silicon/IP vendors.
• Apply Linux networking, DPDK, and RDMA knowledge to debug and optimize performance.
• Document results and advocate design improvements.

Skills

PVT characterization

Python scripting

Lab automation

NIC/SoC bring-up

RDMA protocol knowledge

Linux networking

Schematic interpretation

Data analysis

SerDes familiarity

Education

Bachelor's degree in Computer Science, Computer Engineering, or related field

Advanced degree (MS/PhD) in EE/CE or related field

Tools

Python

Oscilloscopes

BERT/packet analyzers

IPERF/Netperf tooling

SerDes lab equipment

Job description

Meta's Infrastructure team delivers scalable and reliable custom ASIC solutions to meet Meta's data center needs. Ramping to production and solving data center scaling and deployment challenges requires a systems-based approach to silicon bring-up and validation.

The team works on productization: early architecture and design inputs, pre-silicon validation on emulation platforms, first-silicon bring-up, and post-silicon characterization across process, voltage, and temperature corners. We write tests, build bare-metal environments and reusable frameworks that scale from pre-silicon platforms to large fleets of ASICs in the lab, and we build and maintain extensive lab automation to do it at volume and velocity.

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 12+ years of relevant industry experience Demonstrated hands-on validation and characterization experience on complex ASICs, SoCs, NICs, or high-speed interfaces Proven experience with PVT (Process / Voltage / Temperature) characterization Ability to read and reason about schematics and either power delivery networks or high-speed interface implementations Proficiency in Python for test development, lab automation, and/or data analysis Hands-on lab experience with domain-relevant instrumentation Experience taking a custom NIC or networking ASIC from first silicon through high-volume production Experience working directly with ODMs and silicon/IP vendors Hands-on lab experience with domain-relevant instrumentation for Networking - traffic generators, protocol analyzers, high-speed scopes/BERTs, optics and cabling, switches; plus RDMA (RoCE and/or InfiniBand) at the protocol and debug level, Ethernet performance tooling (iperf, netperf, packet capture and analysis), and both front-end and back-end NICs and their differing traffic and scaling models Experience with Linux networking internals, kernel/userspace drivers, and DPDK or verbs‑level programming Advanced degree (MS or PhD) in Electrical Engineering, Computer Engineering, or a related field Familiarity with SerDes tuning, link margining, FEC, and errata characterization Experience building large‑scale lab automation frameworks and characterization data pipelines Experience with AI/HPC back-end fabrics and collective communication traffic patterns