Technical Director, Packaging Engineering (AI2557)

SiMa.ai, Inc.; San Jose (CA); On-site; USD 231,000 - 358,000; Full time

Benefits offered by this job

Private equity

Benefits package

Job summary

SiMa.ai, Inc. seeks a Technical Director of Packaging Engineering in San Jose, CA to lead high-speed packaging development for LPDDR5x/6, PCIe Gen5, and related interfaces.

You will own SI/PI design, lab correlation, and supplier relationships, driving architecture through mass production with a focus on cost, quality, and reliability. The role requires hands-on experience with advanced substrates, 2.5D/Chiplet concepts, and cross-functional leadership across Design, Hardware, and QA teams.

Qualifications

• Hands-on SI/PI design and simulation for high-speed DRAM (LPDDR5x/6) and PCIe Gen5.
• Experience with UCIe channels and PDN at package and board level, with lab correlation.
• Package substrate design including bump/ball map and stack-up.
• SiP experience with multi-die and memory integration; related assembly challenges.
• Proven OSATs and substrate supplier management from design through mass production.
• Automotive package qualification and NPI-to-mass-production experience (AEC-Q100, PPAP).
• Strong understanding of high-speed mixed-signal FCBGA packaging development.

Responsibilities

• Own SI/PI for high-speed interfaces - LPDDR5x/6, PCIe Gen5, 10G Ethernet, MIPI.
• Lead package development from architecture to mass production, balancing cost and quality.
• Define and implement FCBGA and SiP packaging strategies with cross-functional teams.
• Drive OSAT and substrate supplier relationships, negotiations, and qualification roadmaps.
• Oversee packaging NPI including characterization and board-level reliability.
• Manage package production control, issues resolution, and yield improvement.
• Support RMA and FA activities with QA and Design teams.
• Represent Packaging Engineering to customers and lead a design team.

Skills

SI/PI design

High-speed interfaces

LPDDR5x/6

PCIe Gen5

Channel & PDN simulation

Lab correlation

Package architecture

Thermo-mechanical design

coordination with Design, Hardware &Q

Education

BS/MS in Electrical/Mechanical/Materials

Tools

Ansys HFSS/SIwave

Cadence Sigrity/Clarity

Keysight ADS

Cadence APD+/SiP Layout

Job description

Job Title: Technical Director, Packaging Engineering

Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office)

Job ID: AI2557

Job Description

SiMa.ai is looking for a Technical Director of Packaging Engineering to drive High Performance FCBGA and SiP packaging technology development to support SiMa.ai MLSoCTM IC roadmap from package definition and design through qualification to mass production. This is a hands-on technical leadership role with personal ownership of package design and SI/PI for high-speed LPDDR and PCIe interfaces.

The candidate will be responsible for packaging strategy and OSAT/substrate supplier relationships, directing, and coordinating all packaging activities to develop the package and ramp it up to high-volume production, ensuring world-class product quality, capacity and best possible cost.

Key Responsibilities:

Areas of focus and key responsibilities (include, but not limited to):

• Own package SI/PI hands-on for high-speed interfaces - LPDDR5x/6 DRAM and PCIe Gen5, plus 10G Ethernet and MIPI: chip-package-board co-design, channel and PDN simulation (loss, crosstalk, eye margin, PDN impedance, IR drop), and lab correlation
• Lead and coordinate advanced package development activities from package definition (architecture, bump/ball map, substrate stack-up, body size) and design to mass production, including all aspects of high density/high performance interconnects design, thermo-mechanical (warpage, lid/stiffener, thermal), quality, reliability, cost, and yield constraints
• Definition and implementation of FCBGA and SiP packaging strategies for high-speed complex mixed-signal ICs in close collaboration with Design, Hardware, and Quality teams
• Drive OSAT and substrate supplier relationships: selection, technical and commercial negotiation, capacity, process and material qualification, PCN review, and yield/cost roadmaps
• Packaging NPI activities including characterization, qualification (JEDEC, AEC-Q100, board-level reliability) and productization at the right cost and quality for tier-1 customers, including Automotive
• Package production control, issues resolution, yield/DPPM monitoring and improvement
• Support package RMA and FA activities, working closely with QA and Design teams
• Representing Packaging Engineering to SiMa.ai customers
• Build and lead a compact package design and SI/PI team as a player-coach, personally reviewing layouts and simulation results
• Travel up to 10%

Required Background

• BS/MS in Electrical Engineering, Mechanical Engineering, Material Science or a related field with 10+ years relevant experience in FCBGA/SiP package design and development
• Must have: hands-on SI/PI design and simulation of high-speed DRAM (LPDDR5x/6), PCIe (Gen5), UCIe channels and PDN at package and board level, using tools such as Ansys HFSS/SIwave, Cadence Sigrity/Clarity, or Keysight ADS, with lab correlation (VNA/TDR, eye measurements)
• Hands-on package substrate design: bump/ball map, stack-up, routing, and design-rule trade-offs with substrate vendors (Cadence APD+/SiP Layout or equivalent)
• SiP experience: multi-die and SoC-plus-memory integration, passive integration, and the related assembly and test challenges
• Proven track record driving OSATs and substrate suppliers from package definition through qualification and mass production
• Automotive package qualification and NPI-to-mass-production experience (AEC-Q100, PPAP)
• Good understanding and hands-on experience of all aspects of complex high-speed mixed-signal SoC High Performance FCBGA packaging development, cost and quality
• Proficiency with thermal, mechanical, reliability and cost trade-offs in package design
• Experience with FCBGA failure mechanisms and failure analysis
• Experience with advanced substrate materials with low dielectric constant (Dk), low dielectric loss (Df), and low coefficient of thermal expansion (CTE) at high frequencies to solve problems such as transmission loss and package warpage
• Excellent verbal and written communication and presentation skills
• Fluent in English

Desired Qualifications and Skills:

• Familiarity with 2.5D and Chiplet technologies
• Package-board co-design for modules and PCIe add-in cards

Personal Attributes

• Can-do attitude with a strong sense of ownership and accountability.
• Strong team player who collaborates effectively across functions.
• Curious, creative, and resourceful problem solver.
• Execution-and results-oriented.
• Self-driven and proactive.
• Thinks strategically and takes a broader business perspective.
• Strong interpersonal and communication skills.
• Highly accountable with a strong commitment to delivering results.

The annual salary for this position ranges from $231,100 - $358,200. The actual annual salary offered will depend on several factors, including - among others - job-related skills, experience, technical expertise, qualifications, work location, and business needs. The annual salary range for this position is subject to change and may be adjusted in the future.

In addition to base salary, this role is also eligible for private company equity, and a comprehensive package of employee benefits. Please note that the salary ranges listed for U.S. roles reflect base salary only and do not include equity or other forms of compensation.

EEO Employer: SiMa is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.