System Technology Research Engineer - (PhD Intern)

Intel; Santa Clara (CA); On-site; USD 50,000 - 73,000; Full time

Job summary

Intel in Santa Clara is seeking a Research Engineer Intern to help develop STCO methodology and evaluate 3D/2.5D dis-aggregation schemes using solder microbumps or hybrid bonding for memory and logic stacking across product architectures.

You will collaborate with diverse teams across packaging and semiconductor processing to drive innovation, contributing to Intel's roadmap and gaining hands-on experience with cutting-edge technologies.

Qualifications

• PhD candidacy in Electrical/Electronics Engineering or Computer Architecture.
• 1–2+ years of research experience relevant to system architecture modelling, digital circuit analysis and design, VLSI physical layout, or multi-physics modeling.
• Familiarity with IC design and physical layout tools such Cadence Virtuoso or Synopsis Fusion Compiler.

Responsibilities

• Develop and refine STCO methodologies.
• Assess system-level performance of novel devices, interconnects, patterning, materials, systems and integration schemes.
• Collaborate with cross-functional teams to drive innovation across packaging and semiconductor processing.

Skills

Analytical and problem-solving

Organized and efficient

Collaborative and team-oriented

Flexible and adaptable

Strong communicator

Education

PhD candidacy in Electrical/Electronics Engineering or Computer Architecture

Tools

Cadence Virtuoso

Synopsis Fusion Compiler

Job description

Job Details

Job Description:

Position Overview

As a Research Engineer Intern, you will play a crucial role in developing STCO methodology and evaluating 3D/2.5D dis-aggregation schemes using solder microbumps or hybrid bonding for memory and logic stacking across different product architectures. This internship offers a unique opportunity to work on pioneering technologies and contribute to Intel's semiconductor processing and packaging roadmap.

What You'll Do

• Develop and enhance STCO methodologies.
• Perform system-level evaluations of novel devices, interconnects, patterning, materials, systems, and integration schemes.
• Collaborate with diverse teams to drive innovation across various applications.

Who We're Looking For

• Driven and Motivated; a self-starter who thrives in a dynamic environment and is committed to delivering high-quality results.
• Analytical and Problem-Solving Skills: Ability to tackle complex challenges with a strategic approach.
• Organized and Efficient: Strong prioritization and time management skills to handle a fast-paced workflow.
• Collaborative and Team-Oriented: Excellent stakeholder management and teamwork ethics.
• Flexible and Adaptable: Comfortable working in an agile environment with a tolerance for ambiguity.
• Strong Communicator: Good interpersonal skills to facilitate effective collaboration and communication

Internship Details

Minimum of 3 months during summer 2026, with potential for extension based on business needs.

Why Choose Intel?

• Collaborate with industry leaders and innovators.
• Gain hands-on experience with cutting-edge technologies.
• Contribute to projects that shape the future of semiconductor processing.

Qualifications

Minimum Qualifications

• Active Ph.D. candidacy in one of the following areas of study: Electrical Engineering, Electronics Engineering, Computer Architecture and Design or similar.
• 1-2+ years research experience relevant to one or more of the following areas: System architecture modelling, digital circuit analysis and design, VLSI physical layout, electronic design automation, multi-physics modeling of electronic materials or systems.
• Familiarity with IC design and physical layout tools such Cadence Virtuoso or Synopsis Fusion Compiler.

Preferred Qualifications

• System architecture design and modelling
• IC design, simulation, physical layout and tapeout experience.
• Familiar with DRAM and SRAM circuit design and layout
• Familiar with integrated circuits manufacturing flow and requirements
• Familiar with different 2.5D and 3D packaging technologies
• 3DIC design and simulation experience