3D IC Packaging Research Engineer Intern

Intel; Santa Clara (CA); On-site; USD 50,000 - 73,000; Full time

Job summary

Intel in Santa Clara is seeking a Research Engineer Intern to help develop STCO methodology and evaluate 3D/2.5D dis-aggregation schemes using solder microbumps or hybrid bonding for memory and logic stacking across product architectures.

You will collaborate with diverse teams across packaging and semiconductor processing to drive innovation, contributing to Intel's roadmap and gaining hands-on experience with cutting-edge technologies.

Qualifications

• PhD candidacy in Electrical/Electronics Engineering or Computer Architecture.
• 1–2+ years of research experience relevant to system architecture modelling, digital circuit analysis and design, VLSI physical layout, or multi-physics modeling.
• Familiarity with IC design and physical layout tools such Cadence Virtuoso or Synopsis Fusion Compiler.

Responsibilities

• Develop and refine STCO methodologies.
• Assess system-level performance of novel devices, interconnects, patterning, materials, systems and integration schemes.
• Collaborate with cross-functional teams to drive innovation across packaging and semiconductor processing.

Skills

Analytical and problem-solving

Organized and efficient

Collaborative and team-oriented

Flexible and adaptable

Strong communicator

Education

PhD candidacy in Electrical/Electronics Engineering or Computer Architecture

Tools

Cadence Virtuoso

Synopsis Fusion Compiler

Job description

Intel in Santa Clara is seeking a Research Engineer Intern to help develop STCO methodology and evaluate 3D/2.5D dis-aggregation schemes using solder microbumps or hybrid bonding for memory and logic stacking across product architectures.

You will collaborate with diverse teams across packaging and semiconductor processing to drive innovation, contributing to Intel's roadmap and gaining hands-on experience with cutting-edge technologies.