Hybrid Research Engineer Intern - STCO & 3D Packaging

Intel; Austin (TX); Hybrid; USD 142,000 - 143,000; Part time

Benefits offered by this job

Hybrid work model

Stock bonuses

Health benefits

Job summary

Intel's Foundry System Technology team seeks a Research Engineer Intern to advance STCO methodology and evaluate 3D/2.5D dis-aggregation schemes using solder microbumps or hybrid bonding across memory and logic stacking.

You will collaborate with diverse teams, perform system-level evaluations of devices and interconnects, and contribute to Intel's semiconductor processing and packaging roadmap during a 3‑month minimum internship.

Qualifications

• Active Ph.D. candidacy in Electrical Engineering, Electronics Engineering, Computer Architecture and Design or similar.
• 1–2+ years research experience relevant to system architecture modelling, digital circuit analysis and design, VLSI physical layout.
• Familiarity with IC design and physical layout tools such Cadence Virtuoso or Synopsis Fusion Compiler.

Responsibilities

• Develop and enhance STCO methodologies.
• Perform system-level evaluations of novel devices, interconnects, patterning, materials, systems, and integration schemes.
• Collaborate with diverse teams to drive innovation across various applications.

Skills

Research experience

IC design tools

Analytical thinking

Education

Active Ph.D. candidacy in EE/EC/Computer Architecture

Tools

Cadence Virtuoso

Synopsys Fusion Compiler

Job description

Intel's Foundry System Technology team seeks a Research Engineer Intern to advance STCO methodology and evaluate 3D/2.5D dis-aggregation schemes using solder microbumps or hybrid bonding across memory and logic stacking.

You will collaborate with diverse teams, perform system-level evaluations of devices and interconnects, and contribute to Intel's semiconductor processing and packaging roadmap during a 3‑month minimum internship.