STCO Research Engineer Intern - 3D/2.5D Packaging

Intel; Austin (TX); Hybrid; USD 142,000 - 143,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Job summary

Intel's Foundry System Technology team seeks an Research Engineer Intern to help advance STCO methodologies and evaluate 3D/2.5D dis-aggregation schemes using solder microbumps or hybrid bonding for memory and logic stacking. You will collaborate across teams to push semiconductor innovations.

The role offers a hands-on internship with exposure to cutting-edge packaging technologies, DRAM/SRAM considerations, and industry-leading processes in a hybrid work model.

Qualifications

• Active Ph.D. candidacy in the specified fields.
• 1-2+ years of research experience in system architecture modelling, digital circuit analysis/design, VLSI layout, EDA, or multi-physics…
• Familiarity with IC design and physical layout tools such Cadence Virtuoso or Synopsis Fusion Compiler.

Responsibilities

• Develop and enhance STCO methodologies.
• Perform system-level evaluations of devices, interconnects, patterning, materials, systems, and integration schemes.
• Collaborate with diverse teams to drive innovation across applications.

Skills

Research experience

Python programming

Analytical skills

Education

Active Ph.D. candidacy in Electrical Engineering / Electronics Engineering / Computer Architecture and Design

Tools

Cadence Virtuoso

Synopsis Fusion Compiler

Job description

Intel's Foundry System Technology team seeks an Research Engineer Intern to help advance STCO methodologies and evaluate 3D/2.5D dis-aggregation schemes using solder microbumps or hybrid bonding for memory and logic stacking. You will collaborate across teams to push semiconductor innovations.

The role offers a hands-on internship with exposure to cutting-edge packaging technologies, DRAM/SRAM considerations, and industry-leading processes in a hybrid work model.