System IP Design Verification Engineer

Canvendor; San Jose (CA); On-site; USD 129,000 - 241,000; Full time

Job summary

An established industry player is seeking a Senior Staff System IP Design Verification Engineer for an exciting role in San Jose, CA. This position involves hands-on project execution and contributions to the functional verification of System IP, including coherent interconnect and caches. The ideal candidate will have extensive experience in design verification, with a strong background in creating test plans, debugging, and collaborating with cross-functional teams. Join a dynamic team and take part in innovative projects that shape the future of technology. If you're passionate about engineering and ready to make an impact, this opportunity is for you.

Qualifications

• 12+ years of experience in a design verification role.
• Expert coding skills in Testbench, Stimulus, and coverage closure.
• Experience with ARM protocols like CHI, AXI.

Responsibilities

• Architect and build reusable testbenches from scratch.
• Drive best practices and methodologies to improve productivity.
• Collaborate with designers to verify design correctness.

Skills

Design Verification

System Verilog

UVM

Testbench Development

Gate Level Simulation

Python Scripting

Communication Skills

Education

PhD in Electrical Engineering

MS in Electrical Engineering

BS in Electrical Engineering

Tools

Git

Unix

Perl

Python

Job description

3 days ago Be among the first 25 applicants

Direct message the job poster from Canvendor

IT & Engineering Recruiter at Canvendor | Hiring for Fulltime/Contract Consultants. Drop your Resume E: [e-mail]

We do have a System IP Design Verification Engineer role in Austin, TX/San Jose, CA (Onsite). Please find the Job Description below and kindly respond back with your updated resume.

Job Location: Austin, TX/San Jose, CA (Onsite)

Duration: 12+ Months

Job Description

As a Senior Staff System IP Design Verification Contractor you will contribute to the functional verification of System IP including coherent interconnect and caches. This is a technical individual contributor role with heavily involved hands-on project execution. A strong background in Design Verification and hands-on experience with both block-level and top-level is required to be successful in this role.

Key responsibilities:

• Architecting and building re-usable testbenches right from scratch
• Proposing and driving best practices/methodologies/automation that can improve productivity
• Owning key features and timely execution of tasks as per milestones
• Experience with GLS [gate level simulation]
• Creating test plans as per spec and presenting to various stakeholders
• Working with designers to resolve any spec issues
• Creating test benches, verification environments, stimulus, tests
• Collaborating with designers to verify the correctness of a design feature, and resolve fails
• Developing assertions, checkers, covergroups, Systemverilog constraints
• Debugging and root causing functional fails from regressions
• Analyzing code and functional coverage results, performing gap analysis
• Working with SoC team to debug functional fails during IP bringup and feature execution
• Collaborating with Physical design teams, running and debugging gate-level simulations
• Collaborating with Performance verification teams to help with co-sim TB bringup
• Bringup power-aware verification with UPF
• Helping with Silicon bringup and root causing fails
• Phd/MS/BS in Electrical or Computer Engineering
• 12+ years industry experience in a design verification role
• Expert hands-on coding skills in Testbench, Stimulus, checkers development, coverage closure.
• Experience with System Verilog, UVM or equivalent
• Knowledge of ARM protocols or equivalent protocols – CHI, AXI, ACElite, APB
• Experience with Git version control, Unix/Perl/Python scripting
• Good written and verbal communication skills
• Experience with GLS, power vector generation
• Formal verification skills will be a plus

Combined experience with coherent interconnect, caches and LPDDR memory controllers will be a plus

Seniority level

• Seniority level

  Mid-Senior level

Employment type

• Employment type

  Contract

Job function

• Industries

  Semiconductor Manufacturing

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