Synthesis-DFT Stitch CAD Engineer

Qualcomm; San Diego (CA); On-site; USD 164,000 - 246,000; Full time

Benefits offered by this job

RSU grants

Annual discretionary bonus

Comprehensive benefits package

Job summary

Qualcomm Technologies Inc’s Global CAD team is seeking an expert CAD engineer to advance gate‑level synthesis and DFT stitch flows for Snapdragon chips powering billions of devices. The role requires exposure to synthesis, DFT, placement and routing, CAD development, and collaboration with design teams to shorten cycles and boost PPA.

Qualcomm leverages leading edge internal and EDA tech in implementation, including genAI/ML, automation, and PPA recipes for complex multi‑voltage designs, driving

Qualifications

• Bachelor’s degree in Science/Engineering with 6+ years ASIC design/verification/integration/related experience.
• Master’s degree in Science/Engineering with 5+ years ASIC design/verification/integration/related experience.
• PhD in Science/Engineering with 4+ years ASIC design/verification/integration/related experience.

Responsibilities

• Develop Qualcomm DFT stitch flow using Synopsys and Cadence tools.
• Improve SoC synthesis and DFT stitch methods for Snapdragon chips.
• Enable new features from EDA tools for synthesis/DFT checks.
• Handle complex multi‑voltage crossings on DFT paths.
• Support Snapdragon design teams and address requests via tickets.
• Interface with EDA vendors to enable production-ready tool sets.
• Maintain regression of complex DFT stitch and synthesis test cases.
• Innovate to reduce area, dynamic power, and turnaround time; contribute to patents.

Skills

VLSI CAD experience

Python

TCL

Education

Bachelor’s degree in Science/Engineering

Master’s degree in Science/Engineering

PhD in Science/Engineering

Tools

Synopsys tools

Cadence tools

Job description

Job Overview

Join Qualcomm Technologies Inc’s vibrant Global CAD team pushing the limits of gate‑level synthesis and DFT stitch solutions for Snapdragon chips powering billions of mobile devices. The position requires exposure to synthesis, DFT, placement and routing, CAD development skills, and collaboration with design teams to shorten design cycles and deliver PPA improvements.

Qualcomm is using leading‑edge internal and EDA technologies in the implementation domain, including pioneering in genAI/ML, and developing good‑by‑construction automation and PPA recipes for the most complex designs in terms of multi‑voltage and Fmax‑area‑power goals.

Responsibilities

• Participate in developing Qualcomm DFT stitch flow and methods, leveraging Synopsys and Cadence solutions and tools.
• Improve SoC synthesis and DFT stitch methodologies for diverse Mobile, Compute, AI, IoT Snapdragon chips.
• Enable new features from EDA tools or internal tools for synthesis and DFT stitch checks.
• Develop and support methodology to handle complex multi‑voltage crossings on DFT paths.
• Support Snapdragon design teams on CAD solutions, analyze requests, and address them through ticket queues.
• Interface with EDA vendors to enable production‑ready tool sets that satisfy project requirements.
• Set up, augment, and maintain a regression of complex DFT stitch and synthesis test cases.
• Innovate with design, tool, and flow techniques for area reduction, dynamic power reduction, and turnaround time; contribute to patents.

Preferred Qualifications

• Bachelor of Masters degree or PhD in Computer Engineering, Electrical Engineering, or related field.
• 5–10 years of experience in VLSI CAD, preferably synthesis, DFT, and P&R.
• 5–10 years of experience with scripting tools and programming languages: Python and TCL preferred.

Principal Duties and Responsibilities

• Enable synthesis and DFT stitch flows for advanced process nodes.
• Lead EDA vendor roadmap on DFT stitch techniques with Snapdragon DFT and implementation teams.
• Work with Qualcomm’s AI team on R&D initiatives to reduce die area, dynamic power, performance, and turnaround time.
• Deep‑dive on implementation issues such as cell legalization, congestion hotspots, and DFT stitch failures.
• Interface and drive EDA vendor application engineers to resolve block convergence problems faced by design teams.

Minimum Qualifications

• Bachelor’s degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
• Master’s degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

EEO Statement

Qualcomm is an equal‑opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. To request accommodations, email disability‑[e-mail] or call Qualcomm’s toll‑free number.

Pay Range and Other Compensation & Benefits

$164,000.00 – $246,000.00. The salary range reflects the broad minimum to maximum pay scale for this job code at the posted location. Additional compensation includes a competitive annual discretionary bonus program, RSU grants for eligible employees, and a comprehensive benefits package designed to support success at work, at home, and at play.