Synthesis & DFT Stitch CAD Engineer for SoC Optimization

Qualcomm; San Diego (CA); On-site; USD 164,000 - 246,000; Full time

Benefits offered by this job

RSU grants

Annual discretionary bonus

Comprehensive benefits package

Job summary

Qualcomm Technologies Inc’s Global CAD team is seeking an expert CAD engineer to advance gate‑level synthesis and DFT stitch flows for Snapdragon chips powering billions of devices. The role requires exposure to synthesis, DFT, placement and routing, CAD development, and collaboration with design teams to shorten cycles and boost PPA.

Qualcomm leverages leading edge internal and EDA tech in implementation, including genAI/ML, automation, and PPA recipes for complex multi‑voltage designs, driving

Qualifications

• Bachelor’s degree in Science/Engineering with 6+ years ASIC design/verification/integration/related experience.
• Master’s degree in Science/Engineering with 5+ years ASIC design/verification/integration/related experience.
• PhD in Science/Engineering with 4+ years ASIC design/verification/integration/related experience.

Responsibilities

• Develop Qualcomm DFT stitch flow using Synopsys and Cadence tools.
• Improve SoC synthesis and DFT stitch methods for Snapdragon chips.
• Enable new features from EDA tools for synthesis/DFT checks.
• Handle complex multi‑voltage crossings on DFT paths.
• Support Snapdragon design teams and address requests via tickets.
• Interface with EDA vendors to enable production-ready tool sets.
• Maintain regression of complex DFT stitch and synthesis test cases.
• Innovate to reduce area, dynamic power, and turnaround time; contribute to patents.

Skills

VLSI CAD experience

Python

TCL

Education

Bachelor’s degree in Science/Engineering

Master’s degree in Science/Engineering

PhD in Science/Engineering

Tools

Synopsys tools

Cadence tools

Job description

Qualcomm Technologies Inc’s Global CAD team is seeking an expert CAD engineer to advance gate‑level synthesis and DFT stitch flows for Snapdragon chips powering billions of devices. The role requires exposure to synthesis, DFT, placement and routing, CAD development, and collaboration with design teams to shorten cycles and boost PPA.

Qualcomm leverages leading edge internal and EDA tech in implementation, including genAI/ML, automation, and PPA recipes for complex multi‑voltage designs, driving