Staff SoC DFT Engineer, HBM

1000 Micron Technology, Inc.; Richardson (TX); On-site; USD 120,000 - 150,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Income protection programs

Paid family leave

Robust paid time-off program

Paid holidays

Job summary

1000 Micron Technology, Inc. is seeking an experienced SoC Design for Test (DFT) Engineer. You will be responsible for owning the DFT architecture and implementation for HBM designs, ensuring alignment with integration, timing, and physical requirements.

The role requires strong hands-on experience in SoC design for test, with a focus on DFT flows. Candidates should possess a Bachelor’s degree in Electrical Engineering and seven years of relevant experience. Comprehensive benefits are offered, including healthcare plans and paid time off.

Qualifications

• Strong hands-on experience with DFT architecture and implementation.
• Seven or more years of relevant experience in SoC design or DFT.
• Experience working across full RTL-to-GDS SoC flows.

Responsibilities

• Own SoC-level design for test (DFT) architecture and implementation.
• Define DFT architecture early in the design cycle.
• Collaborate with physical design teams to optimize DFT solutions.

Skills

SoC design for test (DFT)

MBIST/LBIST concepts

Boundary scan (JTAG)

RTL debugging

Scripting languages (Python, Tcl, Perl)

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field

Tools

EDA tools from Siemens, Synopsys, and/or Cadence

Job description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Responsibilities

• Own SoC‑level design for test (DFT) architecture and implementation, including scan, memory built‑in self‑test (MBIST), logic built‑in self‑test (LBIST) where applicable, boundary scan (Joint Test Action Group, JTAG), and test access architectures for HBM base‑die designs.
• Define and drive DFT architecture early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design requirements.
• Implement and integrate DFT logic at block, subsystem, and full‑chip levels while partnering closely with register‑transfer level (RTL) design and SoC integration teams.
• Execute and sign off DFT flows, including linting, clock‑domain crossing (CDC) checks, DFT rule checks, automatic test pattern generation (ATPG) readiness, and coverage closure.
• Collaborate with physical design teams to optimize DFT solutions for placement, routing, timing closure, and design rule check/layout versus schematic (DRC/LVS) sign‑off.
• Work with verification, product engineering, test, probe, and manufacturing teams to ensure testability, diagnosability, smooth pre‑silicon debug, and post‑silicon bring‑up.
• Partner with computer‑aided design (CAD) and methodology teams to standardize and improve DFT flows, contribute to cross‑group technical reviews, mentor engineers as appropriate, and drive innovation for future HBM generations.

Minimum Qualifications

• Strong hands‑on experience with SoC design for test (DFT) architecture and implementation, including scan insertion, MBIST/LBIST concepts, boundary scan (JTAG), and ATPG.
• Experience working across full RTL‑to‑GDS SoC flows and collaborating with synthesis, static timing analysis (STA), and physical design teams.
• Proficiency using industry‑standard electronic design automation (EDA) tools from Siemens, Synopsys, and/or Cadence for DFT and implementation.
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
• Seven or more years of relevant experience in SoC design, DFT, or implementation for complex digital application‑specific integrated circuits (ASICs) or SoCs.

Preferred Qualifications

• Experience with large, complex SoCs that integrate multiple intellectual property (IP) blocks and subsystems.
• Strong RTL debugging, design analysis, and problem‑solving skills.
• Experience using scripting languages such as Python, Tcl, or Perl for flow automation.
• Ability to communicate clearly and collaborate effectively across global, cross‑functional teams.
• Familiarity with memory systems such as dynamic random‑access memory (DRAM), high‑bandwidth memory (HBM), and related JEDEC specifications.

Benefits

Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time‑off program and paid holidays.

Equal Opportunity and EEO Statement

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.