Staff Semiconductor Device Modeling Engineer

Intel Corporation; Santa Clara (CA); Hybrid; USD 150,000 - 285,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel Corporation in Oregon/Hillsboro and Santa Clara seeks a Staff Device Modeling Engineer to advance circuit modeling for next‑gen semiconductor tech. You will collaborate with cross‑functional teams to develop high‑quality tools aligned with roadmaps and optimized PDK design.

Responsibilities include delivering compact models (FinFET/GAA), performing statistical and RF/EM simulations, and driving validation milestones with Python scripting. Hybrid work model offered.

Qualifications

• Degrees in Electrical Engineering or related field with relevant experience.
• Experience in compact modeling for FinFET/GAAFET devices.
• Experience with script-based data analysis and modeling tools.
• Familiarity with RF and EM simulation workflows.

Responsibilities

• Collaborate with PDK teams to align modeling with roadmaps.
• Validate simulation models and drive milestone readiness.
• Develop compact device models (FinFET, GAA) and assess layout effects.
• Conduct data analysis using Python and related tools.
• Implement benchmarking and Open Model Interface methodologies.
• Coordinate across geographies for integration and optimization.

Skills

Compact modeling techniques

Python scripting

Statistical modeling

RF/EM simulation

HSPICE/Spectre experience

Education

Bachelor’s degree in Electrical Engineering

Master’s degree in Electrical Engineering

Ph.D. in Electrical Engineering

Tools

HSPICE

Spectre

ICCAP

MBP

Job description

Job Details:

Job Description:

The Role and Impact

As a Staff Device Modeling Engineer, you will play a pivotal role in advancing circuit simulation and modeling capabilities for next-generation semiconductor technologies. Your daily responsibilities will include collaborating with cross-functional teams to drive the development of high-quality simulation tools and methodologies, ensuring alignment with technology roadmaps, and enabling optimized solutions for process design kits (PDKs). Your contributions will directly impact accelerating product delivery timelines and enhancing Intel’s leadership in the foundry space.

Business Group

You will be joining Intel’s Design Technology Platform (DTP) organization, a critical pillar that empowers Intel Foundry customers to produce cutting-edge products for the marketplace. The Compact Device Modeling Group (CDMG), within DTP, focuses on co-optimizing Intel’s state-of-the-art process technology and design tools to enable the development of innovative, high-performance products. As part of this team, you will contribute to the modeling solutions that allow design teams to deliver leadership products for data-centric applications faster and with greater precision.

Key Responsibilities

• Partner with technology leaders and PDK teams to ensure modeling capabilities align with roadmap requirements.
• Drive readiness and validation of simulation and modeling solutions to meet PDK delivery milestones.
• Develop compact device models (e.g., FinFET, GAA) for transistor modeling, including layout-dependent effects and circuit performance impacts.
• Conduct statistical modeling, simulation, and data analysis using Python scripting and other relevant tools.
• Implement innovative methodologies for device targeting benchmarking circuits, self-heating effects, and Open Model Interface (OMI) modeling.
• Collaborate across multiple teams and geographies to achieve seamless integration and optimized solutions.

Qualifications:

• Bachelor’s degree in Electrical Engineering or a related discipline with 6+ years of industry experience in the semiconductor field; -OR- Master’s degree in Electrical Engineering or a related discipline with 4+ years of relevant industry experience; -OR- Ph.D. in Electrical Engineering or a related discipline with 2+ years of experience.
• 2+ years of hands-on experience with compact modeling techniques for advanced nodes such as FinFET and GAAFET.
• Proficiency with commercial simulators (e.g., HSPICE, Spectre) and extraction tools (e.g., ICCAP, MBP).
• Experience in Python scripting for data analysis and automation.
• Experience in statistical modeling, RF simulation, and EM simulation.

Preferred Qualifications

• Ph.D. in Electrical Engineering or a related discipline with 3+ years of industry experience in the semiconductor field.
• Strong background in Device physics and RF modeling.
• Experience in RF structure design, RF De-embedding and EM simulation.
• Experience collaborating across teams and geographies, with experience leading technical initiatives.
• Experience with machine learning algorithms and their application in compact model development.
• Strong understanding of process flows, circuit design, and simulation methodologies.

Join us in shaping the future of semiconductor technology innovation.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Oregon, Hillsboro

Additional Locations:

US, California, Santa Clara

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $149,600.00-284,580.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.