Staff Power IC Design Engineer - High-Voltage & Efficiency

1010 Analog Devices Inc.; Chandler (AZ); On-site; USD 150,000 - 210,000; Full time

Job summary

Analog Devices in Chandler, AZ is seeking a Staff Power IC Design Engineer to develop high-performance power management circuits from schematic through silicon validation. You will own block-level design and work with cross-functional teams to deliver robust power solutions.

The role requires an MS EE with 7+ years (PhD with 5+ years also considered), strong transistor-level design skills, Cadence Virtuoso/Spectre, and a track record of tape-out, silicon validation, and production release.

Qualifications

• MSEE with 7+ years of power IC design experience, or PhD with 5+ years (BSEE with equivalent depth considered)
• Strong transistor-level design skills for high-performance power management circuits
• Demonstrated ability to deliver power IC designs through tape-out, silicon validation, and production release
• Solid understanding of BCD, HV-CMOS, and power FET process technologies, including high-voltage device physics and safe operating area constraints
• Proficiency with Cadence IC design suite: Virtuoso, Spectre/APS, and power-stage simulation environments
• Experience with control loop design, compensation techniques, and stability analysis for switching and linear regulators
• Excellent presentation, technical writing, and communication skills

Responsibilities

• Design and implement power management circuit blocks at the transistor level, including DC-DC converters (buck, boost, buck-boost), LDOs, charge pumps, gate drivers, power stages, and protection circuits
• Execute designs from schematic capture through simulation, layout oversight, and post-layout verification
• Perform parasitic-aware simulation, power-stage optimization, and design centering across process corners and operating conditions
• Optimize transient response, loop bandwidth, and load regulation through iterative simulation and bench correlation
• Support silicon bring-up, debug, and correlation of measured results against simulation predictions
• Collaborate with design teams on architecture trade-offs across efficiency, area, EMI, reliability, and cost

Skills

Power IC design

Transistor-level design

Tape-out/silicon validation

Presentation & communication

Education

MSEE with 7+ years

PhD with 5+ years

BSEE with depth

Tools

Cadence Virtuoso

Spectre/APS

Power-stage simulation

Job description

Analog Devices in Chandler, AZ is seeking a Staff Power IC Design Engineer to develop high-performance power management circuits from schematic through silicon validation. You will own block-level design and work with cross-functional teams to deliver robust power solutions.

The role requires an MS EE with 7+ years (PhD with 5+ years also considered), strong transistor-level design skills, Cadence Virtuoso/Spectre, and a track record of tape-out, silicon validation, and production release.