Staff GPU Verification Engineer – Subsystems

Samsung

Austin (TX)

On-site

USD 140,000 - 190,000

Full time

3 days ago
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Job summary

Samsung Austin Research and Development Center seeks a Staff GPU Design Verification Engineer - Subsystems to verify one or more GPU subsystems for the next-generation mobile GPU. You will help develop verification plans, create scalable testbenches with SystemVerilog/UVM, and drive coverage- and sign-off criteria across interfaces.

The role emphasizes debugging, architecture understanding, and collaboration within a global team, contributing to robust verification methodologies and efficient

Qualifications

  • Bachelor's degree in Computer Science or Engineering; or higher degrees with relevant experience.
  • Hands-on GPU/CPU/semiconductor design verification experience.
  • Strong knowledge of computer architecture and GPU subsystem design.
  • Proficient in C/C++, Python, or Perl.
  • Familiarity with SystemVerilog and UVM, constrained-random testing and coverage.
  • Experience contributing to verification strategy and multi-subsystem verification.
  • Excellent debugging, analytical and communication skills.

Responsibilities

  • Verify one or more GPU subsystems and contribute to verification strategy.
  • Develop verification plans, goals, coverage, and sign-off criteria.
  • Build scalable testbenches using SystemVerilog/UVM and C++.
  • Create constrained-random test scenarios and measure coverage.
  • Debug complex issues spanning multiple blocks and interfaces.

Skills

GPU verification
Computer architecture
C/C++
Python/Perl
SystemVerilog/UVM
Debugging/problem-solving
Communication/collaboration

Education

Bachelors in CS/Engineering
Masters in CS/Engineering
PhD

Tools

SystemVerilog
UVM

Job description

Samsung Austin Research and Development Center seeks a Staff GPU Design Verification Engineer - Subsystems to verify one or more GPU subsystems for the next-generation mobile GPU. You will help develop verification plans, create scalable testbenches with SystemVerilog/UVM, and drive coverage- and sign-off criteria across interfaces.

The role emphasizes debugging, architecture understanding, and collaboration within a global team, contributing to robust verification methodologies and efficient

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