Staff Engineer RTL

Info Way Solutions; San Diego (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Qualcomm is seeking a highly skilled Staff Engineer with strong experience in CPU design, RTL development, and/or Physical Design to work on next-generation high-performance, low-power SoCs and CPU architectures.

The ideal candidate will have hands-on experience in ASIC/SoC development, strong understanding of CPU microarchitecture and digital design, and the ability to work across RTL, synthesis, physical implementation, timing, power, and area optimization.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 4–10 years of experience in ASIC/SoC, CPU, RTL, or Physical Design.
• Hands‑on experience with Verilog/SystemVerilog.
• Strong understanding of digital design and ASIC development flows.

Responsibilities

• Design and optimize high-performance CPU/SoC blocks from microarchitecture through RTL and physical implementation.
• Develop, review, and refine Verilog/SystemVerilog RTL.
• Collaborate with architecture, RTL, design verification, PD, DFT, CAD, Power, and post-silicon teams.
• Mentor junior engineers and contribute to methodology and flow improvements.

Skills

CPU design

Verilog/SystemVerilog

Digital design

ASIC/SoC development

Python

Tcl

Perl

Shell

Linux/Unix

problem-solving

Education

Bachelor's or Master's in Electrical/Computer Engineering or CS

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime STA

Job description

Company: Qualcomm

Experience: 4–10 years

Job Summary

Qualcomm is seeking a highly skilled Staff Engineer with strong experience in CPU design, RTL development, and/or Physical Design (PD) to work on next-generation high-performance, low-power SoCs and CPU architectures.

The ideal candidate will have hands‑on experience in ASIC/SoC development, strong understanding of CPU microarchitecture and digital design, and the ability to work across RTL, synthesis, physical implementation, timing, power, and area optimization. The engineer will collaborate closely with Architecture, RTL, Design Verification, Physical Design, DFT, CAD, Power, and Post‑Silicon teams.

Key Responsibilities

• Design and optimize high-performance CPU/SoC blocks from microarchitecture through RTL and physical implementation.
• Develop, review, and refine Verilog/SystemVerilog RTL.
• Participate in microarchitecture definition and design trade‑offs targeting Power, Performance, and Area (PPA).
• Work closely with Physical Design teams on synthesis, floorplanning, placement, CTS, routing, timing closure, and signoff.
• Analyze and resolve timing, congestion, power, area, and design‑closure issues.
• Support RTL-to-GDS implementation and identify RTL changes required for physical convergence.
• Perform or support STA/MMMC analysis, constraint development, and timing optimization.
• Collaborate with verification teams on functional verification, coverage, debugging, and design quality.
• Work with DFT, CAD, and implementation teams to resolve complex design issues.
• Develop automation and productivity solutions using Python, Tcl, Perl, or Shell.
• Participate in design reviews and provide technical leadership on critical design problems.
• Mentor junior engineers and contribute to methodology and flow improvements.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 4–10 years of experience in ASIC/SoC, CPU, RTL, or Physical Design.
• Strong understanding of digital design and ASIC development flows.
• Hands‑on experience with Verilog/SystemVerilog.
• Strong understanding of CPU/microprocessor architecture is highly preferred.
• Experience with one or more of:
• Synthesis
• Physical Design
• Static Timing Analysis
• Timing closure
• PPA optimization
• SoC integration
• Experience working in Linux/Unix environments.
• Strong scripting/programming skills in Python, Tcl, Perl, or Shell.
• Strong debugging, analytical, and problem‑solving skills.

Preferred Qualifications

CPU / RTL

• Experience with CPU pipeline architecture, including Fetch, Decode, Rename, Execute, Load/Store, Cache, MMU, or Branch Prediction.
• Experience with out-of-order execution, memory hierarchy, or processor microarchitecture.
• Strong RTL coding and microarchitecture implementation experience.
• Knowledge of CDC, lint, synthesis, formal verification, and low-power design.

Physical Design

• Experience with complete RTL-to-GDSII flow.
• Floorplanning, power planning, placement, CTS, routing, and timing closure.
• Experience with Cadence Innovus and/or Synopsys Fusion Compiler.
• Experience with PrimeTime STA.
• MMMC timing analysis and advanced-node implementation.
• Experience with IR drop, EM, signal integrity, crosstalk, ECOs, and physical verification.
• Knowledge of UPF and low-power implementation.