Staff ASICS Physical Design Engineer

Anysilicon; San Diego, Northern (CA, KY); Hybrid; USD 140,000 - 200,000; Full time

Job summary

Qualcomm Technologies, Inc. in San Diego is seeking a seasoned engineer to lead and execute timing analysis for complex SoCs across multiple technology nodes.

You will synthesize requirements and drive timing closure in various operating modes, while developing scripts to streamline timing reports and ECO generation. The role requires a Bachelor's in EE/CE/CS and at least seven years of relevant experience, with strong communication and mentoring skills to guide junior engineers in a fast-paced

Qualifications

• Bachelor's degree in EE/CE/CS or related field.
• Seven years of progressive experience in a related occupation.
• Experience in SoC timing analysis and timing closure.

Responsibilities

• Lead timing analysis of complex SoC sub-systems.
• Ensure timing closure across modes and corners.
• Develop scripts/flows for timing reports.
• Mentor junior engineers and share expertise.
• Correlate PNR tools with timing signoff tools.
• Generate ECOs for subsystems and participate in design reviews.

Skills

SoC design expertise

Timing analysis & signoff

Scripting / flows development

Strong analytical skills

Mentoring abilities

Education

Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

PNR tools

Timing signoff tools

Scripted timing reports

Job description

Qualcomm Technologies, Inc. is seeking a highly skilled individual to lead and perform timing analysis for complex sub-systems within the Engineering Group, specifically in ASICS Engineering. This role involves synthesizing ambiguous requirements and ensuring timing closure across various operating modes for premium tier chips utilizing advanced technology nodes such as 14nm, 5nm, 34nm, and 3nm.

Responsibilities:

• Lead timing analysis of complex sub-systems in System-on-Chips (SoC) context.
• Ensure timing closure across various operating modes and corners.
• Conduct clock tree analyses and early planning of pipelines for critical interface timing closure.
• Develop multiple flows/scripts for easy access to timing reports.
• Mentor and train junior team members.
• Perform correlation activities between PNR tools and timing signoff tools.
• Generate Engineering Change Orders (ECOs) for various subsystems.
• Contribute actively in design reviews and project meetings.
• Communicate and implement development plans.

Qualifications:

• Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Seven years of progressive experience in a related occupation.

Skills:

• Expertise in SoC design architecture and methodologies.
• Advanced knowledge in timing analysis and timing signoff processes.
• Proficiency in developing scripts and flows for timing reports.
• Strong analytical and problem-solving skills.
• Excellent communication and mentoring abilities.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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