Sr.Staff SoC Lead design verification Engineer

Qualcomm; Santa Clara (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

An established industry player is seeking a Design Verification Lead to spearhead a talented team of ASIC design verification engineers. In this pivotal role, you will oversee the verification of cutting-edge IP and subsystems for a range of wireless and connectivity devices. Your leadership will guide the development of robust verification processes while collaborating closely with architects and design teams. This role offers a unique opportunity to influence the quality and efficiency of design verification, making a significant impact in the fast-paced world of connectivity technology. If you are passionate about innovation and eager to drive excellence in design verification, this position is tailored for you.

Qualifications

• 8+ years of experience in ASIC design verification with leadership experience.
• Strong skills in System Verilog and UVM methodologies.

Responsibilities

• Lead design verification for Qualcomm WIFI projects and manage a team of engineers.
• Collaborate with cross-functional teams and explore innovative verification methodologies.

Skills

Digital Verification

System Verilog

UVM

Leadership

C/C++

Analytical Skills

Problem-solving

AMBA Bus Protocols

Scripting Languages (Perl, Python)

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

Test Automation Tools

Simulation Tools

Emulation Strategies

Job description

Company:

Qualcomm Atheros, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a Design Verification Lead, you will lead a team of ASIC design verification engineers to verify IP and Subsystems that be integrated in a variety of Qualcomm WIFI, connectivity and IOT devices. You will work closely with SoC Architects, software, validation and design teams to verify IP that meets power, performance and area goals for Qualcomm Wireless and connectivity products. You will lead a team defining the processes, methods and tools for design verification of large complex IP blocks and subsystems.

Job Responsibilities:

1. Lead Sub-System & SoC Design verification for Qualcomm WIFI projects
2. Own end-end low power test bench architecture, test plan and coverage driven verification closure
3. Collaborate with cross geo teams for various IP, SOC and VI deliveries, milestone planning & critical debugs
4. Build, manage and mentor a team of ASIC DV engineers
5. Explore innovative DV methodologies (formal, simulation, and emulation strategies) to continuously push the quality and efficiency of test benches
6. Act as a technical point of contact to the different IP and SoC design teams
7. Provide technical leadership through personal example, mentorship, and strong teamwork

Required Skillset:

1. Experience with various aspects of digital verification such as test automation, code and functional coverage, constraint randomization, system Verilog assertions, and performance.
2. Strong System Verilog / UVM based verification skills, experience with assertions, and coverage-based verification methodology
3. Strong leadership, Analytical and problem-solving skills
4. Experience with C/C++, assembly language.
5. Knowledge of low power design concepts and power management is a big plus.
6. Strong team player and communicator
7. Experience with AMBA bus protocols
8. Experience with GLS, and scripting languages such as Perl, Python is a plus
9. 8+ years or more of practical semiconductor ASIC DV experience including owning end-to-end verification of major SoC blocks
10. 2+ years’ leadership experience taking projects to Tape out

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.

OR

PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.